This application report discusses how the Texas Instruments LM3743 minimizes power consumption during fault conditions thereby reducing thermal loads and increasing reliability.

Using the bq2954 to Charge Multi-Cell (?5-Cell) Li-Ion and LiFePO4 Battery

This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000™ (C6000™) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams

This application report describes a simple low cost low parts-count multiple output DC/DC converterbased on the LM2596 five terminal step-down switching regulator. The circuit described provides multipleoutput voltages (positive and negative) with good regulation using a step-down converter circuit withflyback windings. It uses only one switching regulator IC.

This application report highlights how using external SerDes in conjunction with minimum current driveFPGA I/O can reduce FPGA’s internal noise and reap the benefits of a serial interface across the system.This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have highanalog performance.

While ultimately the decision to use boundary scan test (also know as JTAG or IEEE 1149.1) in a given design should be based on the positive impact to product life-cycle cost, the benefits that accrue

bq2084-V1.40 to bq2084-V1.43 Change List

This document provides analysis details and specific results of the CPU45 errata affecting the following devices:

• MSP430G2744
• MSP430G2544
• MSP430G2344

Often times, embedded processors must be programmed in situations where JTAG is not a viable option for programming the target device. When this is the case, the engineer must rely on some type of se

This application report describes how to interface the DAC8574 digital-to-analog converter to the MSP430F449 mixed signal microcontroller.

In this application report we discuss the hardware and software interface of the TLV1562 10-bit parallel-output analog-to-digital converter (ADC) to the TMS320C54x digital signal processor (DSP). The hardware interface board or evaluation module (EVM) consists of the TLV1562 10-bit ADC a THS5651 10-bit parallel-output communication digital-to-analog converter ((CommsDAC (TM)) and a TLC5618A s

FRAM is a nonvolatile embedded memory technology and is known for its ability to be ultra-low power while being the most flexible and easy-to-use universal memory solution available today. This application report is intended to give new FRAM users and those migrating from flash-based applications knowledge on how FRAM meets key quality and reliability requirements such as data retention and endura

TUSB2136/TUSB3210 Firmware Debugging Guide

This application report examines the thermal performance of different layout techniques for the TPS5461x family of 6-amp synchronous buck regulators. The TPS5461x family consists of the TPS54610 TPS54611 TPS54612 TPS54613 TPS54615 and the TPS54616. The TPS54610 has an adjustable output voltage while the output voltages of the other devices in this family are fixed. This application note is a

The TMS320 DSP C compilers produce several relocatable blocks of code and data when C code is compiled. These blocks are called sections and can be allocated into memory in a variety of ways to conform to a variety of system configurations. The .bss section is used by the compiler for global and static variables. It is one of the default COFF sections that is used to reserve a specified amount of

This application report describes how the G.723.1 Dual-Rate Speech Coder has been implemented on the TMS320C62x digital signal processor (DSP). Beyond the use of the ?C62x intrinsic functions the application report includes specific changes required to allow this coder to operate in a real-time system with other speech coders. Also reported is information on several optimization techniques used t

The TMS320C6472/TMS320TCI6486 has six C64x+ Megamodule cores that run at 500 MHz 625 MHz or 700 MHz. This document has been written based on the performance of the C6472/TCI6486 device running at 500 MHz and 625 MHz. Each megamodule has 32KB of L1D SRAM 32KB of L1P SRAM and 608KB of LL2 SRAM and all six cores share 768KB of SL2 SRAM. A 32-bit 533-MHz DDR2 SDRAM interface is provided on the DSP

This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6454/5 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.

The previous approach specified device timing in terms of data sheet specifications and simulation models. The system designer was