Test results at a TI LVDS Multipoint (LVDM) system show that a VME backplane with an LVDM electrical layer can support signaling rates to 200 Mbps. The performance of differential with the SN65LVDM176 transceiver is characterized using a commercially-available VME card cage. Test results show how changes in bus loading influence the electrical characteristcs of a backplane and the resulting re
As consumers become accustomed to elegant touch interfaces on a variety of devices, these capabilities are becoming more expected on a greater number of devices. The <a href=http://www.ti.com/ww/en/an
This application report explains how to extend the wide output voltage range capability of the TPS6108x by a factor of two using a discrete charge pump.
The reference design and application examples shown in this document help design a TFT-LCD power supply as well as show implementations of power-down sequencing programmable sequencing and boosting output current.
Samples of the Texas Instruments (TI™) TMS320C6201B DSP will be available in the second half of 1998 with volume production starting at the end of the year. The TMS320C6201B revision is manufactured using a 0.18-micron process compared to the currently available revision 2 that uses a 0.25-micron process. The use of a smaller process for the TMS320C6201B DSP will lead to significantly lower
This application report is a general guide for using the CDC7005 clock synchronizer/synthesizer and jitter cleaner from Texas Instruments. This report explains the basic functionality and methods for using the device efficiently along with the results of evaluations. It also describes the clock termination method decoupling the power supply and general applications.
JPEG compression/decompression technique is widely used for still image applications. There are two major ways to implement JPEG algorithm--hardware and software. The hardware approach is good for spe
Cost and performance requirements continue to push the packaging of electronic systems into smaller and smaller spaces. The advent of surface-mount devices has brought pin spacings that differ from on
As intermediate bus voltages decrease, a corresponding increase in line card load currents further complicates the design of power distribution and control sub-systems in networking equipment. As one
This document describes how to link together the GSM full-rate (FR) half-rate (HR) enhanced full-rate (EFR) and adaptive multi-rate (AMR) voice coding implementations on the TMS320C62x(tm) digital signal processor (DSP).
This document helps designers use existing clock-driver products to drive large loads while maintaining a minimum amount of skew between the device outputs. The emphasis of this document is using parallel or ganged outputs to drive loads. A performance evaluation of the CDC201 is provided.