The ADRF5300 is a reflective, SPDT switch manufactured in the silicon process.The ADRF5300 is developed for 5G applications ranging from 24 GHz to 32 GHz. The ADRF5300 has a low insertion loss of 1.1 dB, a high isolation of 38 dB, and an RF input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5300 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V (VDD) applied to the VDD pin. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5300 is packaged in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.APPLICATIONSIndustrial scannerTest instrumentationCellular infrastructure: 5G millimeter waveMilitary radios, radars, electronic counter measures (ECMs)Microwave radios and very small aperture terminals (VSATs)

The ADRF5345 is a high linearity, reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process.The ADRF5345 operates from 1.8 GHz to 3.8 GHz with a typical insertion loss lower than 0.40 dB and a typical input IP3 of 84 dBm. The device has an RF input power handling capability of 39 dBm for continuous wave signals and 39 dBm average and 49 dBm peak for long-term evolution (LTE) signals.The ADRF5345 incorporates an integrated negative voltage generator (NVG) to operate with a single positive supply of 5 V (VDD) applied to the VDD pin drawing a 2 mA supply current. The device employs low voltage complementary metal-oxide semiconductor (LVCMOS)-/low voltage transistor to transistor logic (LVTTL)- compatible controls.The ADRF5345 comes in a 4 mm ? 4 mm, 22-terminal, RoHS-compliant, land grid array (LGA) package and operates between ?40?C to +105?C.APPLICATIONS5G antenna tiltingWireless infrastructureMilitary and high reliability applicationsTest equipmentPin diode replacement

The ADRF5515A is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515A is configured in dual channels with a cascading, two-stage low noise amplifier (LNA) and a high-power silicon singlepole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.05 dB and a high gain of 36 dB at 3.6 GHz, with an output third-order intercept (OIP3) point of 35 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 17 dB of gain at a lower current of 48 mA. In power-down mode, the LNAs are turned off and the device draws 13 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.5 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The device comes in an RoHS-compliant, compact, 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP).APPLICATIONWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems

The ADRF5515 is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515 is configured in dual channels with a cascading, two-stage, LNA and a high power silicon SPDT switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.0 dB and a high gain of 33 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.45 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The ADRF5515 is pin-compatible with the ADRF5545A, 10 W version, which operates from 2.4 GHz to 4.2 GHz.The ADRF5515 does not require any matching components at the RF ports that are internally matched to 50 ?. The ANT and TERM ports are also internally ac-coupled. Therefore, only receiver ports require external dc blocking capacitors.The device comes in an RoHS compliant, compact, 6 mm ? 6 mm, 40-lead LFCSP package.?Applications Wireless infrastructure TDD massive multiple input and multiple output and active antenna systems TDD-based communications systems

The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.?In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (

The ADRF6521 is a dual, fully differential, low noise and low distortion variable gain amplifier (VGA). The high spurious-free dynamic range over the gain range makes the ADRF6521 ideal for communication systems with dense constellations, multiple carriers, and nearby interferers. The VGA has a 21 dB attenuation range with a typical voltage gain of 18 dB. The differential input impedance is 100 ?, while the differential output impedance is 16 ?. The ?1 dB gain flatness bandwidth is 2.5 GHz. The output buffers are capable of swinging 1.5 V p-p into 100 ? loads at >55 dBc for second-order and third-order intermodulation distortion (IMD2 and IMD3), and for second and third harmonic distortion (HD2 and HD3) from low frequency to 1 GHz. Variable output dc offset control is accomplished with the OFS1 and OFS2 pins, and the output common-mode can be controlled with the VOCM pin.The ADRF6521 flexibly operates from a single +5 V supply or from a range of dual supplies and consumes a total supply current of 200 mA. When fully disabled, it consumes 25 mA typical. The ADRF6521 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 20-lead, exposed pad, 3 mm ? 3 mm LFCSP. Performance is specified over the ?40?C to +85?C temperature range.Applications Point-to-point and point-to-multipoint radios Baseband IQ receivers Diversity receivers ADC drivers Instrumentation Medical

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3002 is a complete HDMI?/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports.The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount Pb-free plastic package and is specified to operate over the 0?C to 85?C temperature range.PRODUCT HIGHLIGHTS Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than 20m at data rates up to 3 Gbps. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. EDID replication eliminates the need for multiple EDID EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller. 5 V power combiner powers the EDID replicator and CEC buffer when local system power is off. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control.APPLICATIONS Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes

The ADV3219 and ADV3220 are high speed, high slew rate,buffered, 2:1 analog multiplexers. They offer a ?3 dB signalbandwidth greater than 800 MHz and channel switch times ofless than 20 ns with 1% settling. With ?82 dB of crosstalk and?88 dB isolation (at 5 MHz), the ADV3219 and ADV3220 areuseful in many high speed applications. The differential gain ofless than 0.02% and the differential phase of less than 0.02?,together with 0.1 dB flatness beyond 100 MHz while driving a75 ? back terminated load, make the ADV3219 and ADV3220ideal for all types of signal switching. The ADV3219/ADV3220 include an output buffer that can beplaced into a high impedance state to allow multiple outputs tobe connected together for cascading stages without the off channelsloading the output bus. The ADV3219 has a gain of +1, and theADV3220 has a gain of +2; they both operate on ?5 V supplieswhile consuming less than 7.5 mA of idle current.The ADV3219/ADV3220 are available in the 8-lead LFCSPpackage over the extended industrial temperature range of?40?C to +85?C. Applications Routing of high speed signals including ??Video (NTSC, PAL, S, SECAM, YUV, and RGB) ??Compressed video (MPEG, wavelet) ??3-level digital video (HDB3) Data communications Telecommunications

The ADV3221 and?ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a ?3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than ?58 dB of crosstalk and ?67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The diffe-rential gain error of less than 0.02% and differential phase error of less than 0.02?, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 ? back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching.The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on ?5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 envi-ronment.The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) ? ? Data communications ? ? Telecommunications

The?ADV3221 ?and ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a ?3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than ?58 dB of crosstalk and ?67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The differential gain error of less than 0.02% and differential phase error of less than 0.02?, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 ? back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching.The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on ?5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 envi-ronment.The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) ? ? Data communications ? ? Telecommunications

The ADV3224/ADV3225 are high speed 16 ? 8 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth of greater than 750 MHz and a high slew rate of greater than 2500 V/?s.The ADV3224/ADV3225 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3224 has a gain of +1 and the ADV3225 has a gain of +2, and they both operate on voltage supplies of ?5 V. Channel switching is performed via a serial digital control that can accommodate the daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3224/ADV3225 are available in the 72-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.ApplicationsRouting of high speed signals includingVideo (NTSC, PAL, S, SECAM, YUV, RGB)Compressed video (MPEG, wavelet)3-level digital video (HDB3)Data communicationsTelecommunications

The ADV3226/ADV3227 are high speed 16 ? 16 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth greater than 750 MHz and channel switch times of less than 20 ns with 1% settling.The ADV3226/ADV3227 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3226 has a gain of +1 and the ADV3227 has a gain of +2. They both operate on voltage supplies of ?5 V while consuming only 118 mA (ADV3226) and 133 mA (ADV3227) of idle current. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3226/ADV3227 are available in the 100-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) Data communications Telecommunications

The ADXL204 is a high precision, low power, complete dual-axis accelerometer with signal-conditioned voltage outputs, all on a single monolithic IC. Like the ADXL203, it measures acceleration with a full-scale range of ?1.7 g; however, the ADXL204 is tested and specified for 3.3 V supply voltage, whereas the ADXL203 is tested and specified at 5 V. Both parts function well over a wide 3 V to 6 V operating voltage range. The ADXL204 can measure both dynamic acceleration (for example, vibration) and static acceleration (for example, gravity).The typical noise floor is 170 ?g/?Hz, allowing signals below 2 mg (0.1? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (

The LTC1262 is a regulated 12V, 30mA output DC/DC converter. It is designed to provide the 12V ?5% output necessary to program byte-wide flash memories. The output will provide up to 30mA from input voltages as low as 4.75V without using any inductors. Only four external capacitors are required to complete an extremely small surface mountable circuit.The TTL compatible shutdown pin can be directly connected to a microprocessor and reduces the supply current to less than 0.5?A. The LTC1262 offers improved shutdown current performance and requires fewer external components than competing solutions.The LTC1262 is available in an 8-pin PDIP or SO-8 package.Applications 12V Flash Memory Programming Supplies Compact 12V Op Amp Supplies Battery-Powered Systems

The LTC1550/LTC1551 are switched capacitor charge pump voltage inverters which include internal linear post-regulators to minimize output ripple. Output voltages are fixed at ?4.1V, with ripple voltages typically below 1mVP-P. The LTC1550 is also available in an adjustable output voltage version. The LTC1550/LTC1551 are ideal for use as bias voltage generators for GaAs transmitter FETs in portable RF and cellular telephone applications. The LTC1550/LTC1551 operate from single 4.5V to 6.5V supplies and draw typical quiescent currents of 4.25mA with a 5V supply. Each device includes a TTL compatible Shutdown pin which drops supply current to 0.2?A typically. The LTC1550 Shutdown pin is active low (SHDN), while the LTC1551 Shutdown pin is active high (SHDN). Only four external components are required: an input bypass capacitor, two 0.1?F charge pump capacitors and a filter capacitor at the linear regulator output. The adjustable LTC1550 requires two additional resistors to set the output voltage. The LTC1550/LTC1551 will supply up to 10mA output current with a 5V supply, while maintaining guaranteed output regulation of ?5%. The fixed voltage LTC1550/LTC1551 are available in S0-8 plastic packages. The adjustable LTC1550 is available in a 16-pin SSOP.Applications GaAs FET Bias Generators Negative Supply Generators Battery-Powered Systems Single Supply Applications

DC1012A-C: Demo Board for the LTC2495 16-Bit 8-/16-Channel ΔΣ ADC with PGA, Easy Drive and I2C Interface

DC1017A - Demo Board for: LT5558 - 600MHz to 1100MHz High Linearity Direct Quadrature Modulator

The LTC2928 is a four channel cascadable power supply sequencer and high accuracy supervisor. Sequencing thresholds, order and timing are con?gured with just a few external components, negating the need for PC board layout or software changes during system development. Multiple LTC2928s may be easily connected to sequence an unlimited number of power supplies.Sequence outputs control supply enable pins or N-channel pass gates. Precision input comparators with individual outputs monitor power supply voltages to 1.5% accuracy. Supervisory functions include undervoltage and overvoltage monitoring and reporting as well as ?P reset generation. RST may be forced high to complement margin testing.Application faults, whether internally or externally generated, can shutdown all controlled supplies. The type and source of faults are reported for diagnosis. Individual channel controls are available to independently exercise enable outputs and supervisory functions.A high voltage input allows the LTC2928 to be powered from voltages as high as 16.5V. A buffered reference output permits single negative power supply sequencing and monitoring operations.Applications? Network/Telecom Infrastructure Sequencing for Multiple I/O and Core Voltages Power Management?

The LT1511 current mode PWM battery charger is the simplest, most efficient solution to fast charge modern rechargeable batteries including lithium-ion (Li-Ion), nickel-metal-hydride (NiMH) and nickel-cadmium (NiCd) that require constant-current and/or constant-voltage charging. The internal switch is capable of delivering 3A* DC current (4A peak current). Full-charging current can be programmed by resistors or a DAC to within 5%. With 0.5% reference voltage accuracy, the LT1511 meets the critical constant-voltage charging requirement for Li-Ion cells. A third control loop is provided to regulate the current drawn from the AC adapter. This allows simultaneous operation of the equipment and battery charging without overloading the adapter. Charging current is reduced to keep the adapter current within specified levels. The LT1511 can charge batteries ranging from 1V to 20V. Ground sensing of current is not required and the battery?s negative terminal can be tied directly to ground. A saturating switch running at 200kHz gives high charging efficiency and small inductor size. A blocking diode is not required between the chip and the battery because the chip goes into sleep mode and drains only 3?A when the wall adapter is unplugged.* See LT1510 for 1.5A ChargerApplications Chargers for NiCd, NiMH, Lead-Acid, Lithium Rechargeable Batteries Switching Regulators with Precision Current Limit