The LT3753 is a current mode PWM controller optimized for an active clamp forward converter topology, allowing up to 100V input operation.A programmable volt-second clamp allows primary switch duty cycles above 50% for high switch, transformer and rectifier utilization. Active clamp control reduces switch voltage stress and increases efficiency. A synchronous output is available for controlling secondary side synchronous rectification.The LT3753 is available in a 38-lead plastic TSSOP package with missing pins for high voltage spacings.Applications Industrial, Automotive and Military Systems 48V Telecommunication Isolated Power Supplies

Demonstration circuit 2365A highlights the LTC2358 family of buffered input ADCs. The LTC2358/LTC2357/LTC2353/LTC2333 are low noise, high speed, 16-/18- bit successive approximation register (SAR) ADCs with integrated front end buffers. These ADCs accept a wide common mode range. Pico-amp inputs and high CMRR enable these ADCs to connect directly to a wide range of sensors without compromising measurement accuracy. The demo manual refers to the LTC2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2358-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

The DC2428A is a two-board demonstration system for the LTC2975 Power System Manager and LTM4644-1 quad 4A μModule regulator. The DC2382A contains all the circuitry needed to use the LTC2975 in a power system and control four power supplies. The DC2363A contains four power supplies (LTM4644-1) that the LTC2975 configures and controls. The DC2363A and DC2382A demo boards together provide a sophisticated 4-channel digitally programmable power supply system.

DC242A: Demo Board for the LT1777 Low Noise Step-Down Switching Regulator.

The LT3781 controller simplifies the design of high power synchronous dual transistor forward DC/DC converters. The part employs fixed frequency current mode control and supports both isolated and nonisolated topologies. The IC drives external N-channel power MOSFETs and operates with input voltages up to 72V.The LT3781 is ideal for output derived power schemes, through the use of a large undervoltage lockout hysteresis range. The part is also equipped with an 18V VCC shunt regulator, which prevents exceeding absolute maximum ratings while in trickle start applications.The LT3781?s operating frequency is programmable and can be synchronized up to 350kHz. Switch phase is also controlled during synchronized operation to accommodate multiple-converter systems. Internal logic guarantees 50% maximum duty cycle operation to prevent transformer saturation.The LT3781 is available in a 20-lead SSOP package.Applications Isolated Telecommunication Systems Personal Computers and Peripherals Distributed Power Step-Down Converters Lead Acid Battery Backup Systems Automotive and Heavy Equipment

The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for therequired output rates. A second PLL also operates as an integer-N synthesizer anddrives two LVPECL or LVDS output buffers for 106.25 MHzoperation. No external loop filter components are required, thusconserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm ? 6 mm lead framechip scale package (LFCSP) and can be operated from a single3.3 V supply. The temperature range is ?40?C to +85?C.APPLICATIONSFiber channel line cards, switches, and routersGigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

The AD9575 provides a highly integrated, dual output clockgenerator function including an on-chip PLL core that isoptimized for network clocking. The integer-N PLL design isbased on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize linecard performance. Other applications with demanding phasenoise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltagecontrolled oscillator (VCO), and pin selectable feedback and output dividers.By connecting an external crystal, popular network output frequencies can be locked to the input reference. The output divider and feedback divider ratios are pin programmable for therequired output rates. No external loop filter components are required, thus conserving valuable design time and board space.The AD9575 is available in a 16-lead, 4.4 mm ? 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONS GbE/FC/SONET line cards, switches, and routers CPU/PCI-E applications Low jitter, low phase noise clock generation

The AD9576 provides a multiple output clock generator function comprising two dedicated phase-locked loop (PLL) cores with flexible frequency translation capability, optimized to serve as a robust source of asynchronous clocks for an entire system, providing extended operating life within frequency tolerance through monitoring of and automatic switchover between redundant crystal (XTAL) inputs with minimized switching, induced transients. The fractional-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance, whereas the integer-N PLL provides general-purpose clocks for use as CPU and field-programmable gate array (FPGA) reference clocks.The AD9576 uses pin strapping to select among a multitude of power-on ready configurations for its 11 output clocks, which require only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. These parameters can also be manually configured through a serial port interface (SPI).The AD9576 is packaged in a 64-lead, 9 mm ? 9 mm LFCSP, requiring only a single 2.5 V or 3.3 V supply. The operating temperature range is ?40?C to +85?C.Each OUTx output is differential and contains two pins: OUTx and OUTx. For simplicity, the term OUTx refers to the functional output block containing these two pins..Applications Ethernet line cards, switches, and routers Baseband units SATA and PCI express Low jitter, low phase noise clock generation Asynchronous clock generation

The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Optical networking Test equipmentPRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small, space-saving package. Low Power of 60 mW/Channel at 80 MSPS with Scalable Power Options. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 480 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin Compatible with the AD9257 (14-Bit Octal ADC).

The AD9708 is the 8-bit resolution member of the TxDAC? series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC? family, which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, was specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9708 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS.The AD9708's flexible single-supply operating range of 2.7 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to 45 mW, without a significant degradation in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 20 mW.The AD9708 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families.The AD9708 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 k Ohms output impedance.Differential current outputs are provided to support single-ended or differential applications. The current outputs may be directly tied to an output resistor to provide two complementary, single-ended voltage outputs. The output voltage compliance range is 1.25 V.The AD9708 contains a 1.2 V on-chip reference and reference control amplifier, which allows the full-scale output current to be simply set by a single resistor. The AD9708 can be driven by a variety of external reference voltages. The AD9708's full-scale current can be adjusted over a 2 mA to 20 mA range without any degradation in dynamic performance. Thus, the AD9708 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities.The AD9708 is available in a 28-pin SOIC package. It is specified for operation over the industrial temperature range.

The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multicarrier generation up to their Nyquist frequency. The AD9736 is the 14-bit member of the family, while the AD9735 and the AD9734 are the 12-bit and 10-bit members, respectively. They include a serial peripheral interface (SPI) port that provides for programming of many internal parameters and enables readback of status registers.A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 ?m CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics.Product Highlights Low noise and intermodulation distortion (IMD) features enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz. Double data rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS. Direct pin programmability of basic functions or SPI port access offers complete control of all AD973x family functions. Manufactured on a CMOS process, the AD973x family uses a proprietary switching technique that enhances dynamic performance. The current output(s) of the AD9736 family are easily configured for single-ended or differential circuit topologies.Applications Broadband communications systems Cellular infrastructure (digital predistortion) Point-to-point wireless CMTS/VOD Instrumentation, automatic test equipment Radar, avionics

The AD97481 is an 8-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9748 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9748?s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to 60 mW with a slight degradation in performance by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature-compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 32-lead LFCSP. The AD9748 is the 8-bit member of the pin-compatible TxDAC family, which offers excellent INL and DNL performance. Differential or single-ended clock input (LVPECL or CMOS), supports 210 MSPS conversion rate. Data input supports twos complement or straight binary data coding. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. On-chip voltage reference: The AD9748 includes a 1.2 V temperature-compensated band gap voltage reference.?APPLICATIONS Communications Direct digital synthesis (DSS) Instrumentation

The AD9761 is a complete dual channel, high speed, 10-bitCMOS DAC. The AD9761 has been developed specifically foruse in wide bandwidth communication applications (e.g., spreadspectrum) where digital I and Q information is being processedduring transmit operations. It integrates two 10-bit, 40 MSPSDACs, dual 2x interpolation filters, a voltage reference, anddigital input interface circuitry. The AD9761 supports a20 MSPS per channel input data rate that is then interpolatedby 2x up to 40 MSPS before simultaneously updating eachDAC.The interleaved I and Q input data stream is presented to thedigital interface circuitry, which consists of I and Q latches as wellas some additional control logic. The data is de-interleaved backinto its original I and Q data. An on-chip state machine ensures theproper pairing of I and Q data. The data output from each latch isthen processed by a 2x digital interpolation filter that eases thereconstruction filter requirements. The interpolated output of eachfilter serves as the input of their respective 10-bit DAC.The DACs utilize a segmented current source architecture combinedwith a proprietary switching technique to reduce glitchenergy and to maximize dynamic accuracy. Each DAC providesdifferential current output thus supporting single-ended ordifferential applications. Both DACs are simultaneously updatedand provide a nominal full-scale current of 10 mA. Also,the full-scale currents between each DAC are matched to within0.07 dB (i.e., 0.75%), thus eliminating the need for additionalgain calibration circuitry.The AD9761 is manufactured on an advanced low cost CMOSprocess. It operates from a single supply of 2.7 V to 5.5 V andconsumes 200 mW of power. To make the AD9761 complete italso offers an internal 1.20 V temperature-compensated bandgapreference.PRODUCT HIGHLIGHTS Dual 10-Bit, 40 MSPS DACs A pair of high performance 40 MSPS DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 2x Digital Interpolation Filters Dual matching FIR interpolation filters with 62.5 dB stopband rejection precede each DAC input, thus reducing the DACs? reconstruction filter requirements. Low Power Complete CMOS dual DAC function operates on a low 200 mW on a single supply from 3 V to 5.5 V. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for power reduction during idle periods. On-Chip Voltage Reference The AD9761 includes a 1.20 V temperature-compensated band gap voltage reference. Single 10-Bit Digital Input Bus The AD9761 features a flexible digital interface that allows each DAC to be addressed in a variety of ways including different update rates. Small Package The AD9761 offers the complete integrated function in a compact 28-lead SSOP package. Product Family The AD9761 Dual Transmit DAC has a pair of Dual Receive ADC companion products, the AD9281 (8 bits) and AD9201 (10 bits).

The AD9763/AD9765/AD9767 are dual-port, high speed, 2-channel, 10-/12-/14-bit CMOS DACs. Each part integratestwo high quality TxDAC+? cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/AD9765/AD9767 offer exceptional ac and dc performancewhile supporting update rates of up to 125 MSPS.The AD9763/AD9765/AD9767 have been optimized forprocessing I and Q data in communications applications. Thedigital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.A mode control pin allows the AD9763/AD9765/AD9767 to interface to two separate data ports, or to a single interleavedhigh speed data port. In interleaving mode, the input datastream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACsand updated at half the input data rate.The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See theGain Control Mode section for important date codeinformation on this feature.The DACs utilize a segmented current source architecturecombined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC providesdifferential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide anominal full-scale current of 20 mA. The full-scale currentsbetween each DAC are matched to within 0.1%.The AD9763/AD9765/AD9767 are manufactured on anadvanced, low cost CMOS process. They operate from a singlesupply of 3.3 V to 5 V and consume 380 mW of power.Product HighlightsThe AD9763/AD9765/AD9767 are members of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information.Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%.Low Power. Complete CMOS dual DAC function operates on 380 mW from a 3.3 V to 5 V single supply. The DAC full-scalecurrent can be reduced for lower power operation, and a sleepmode is provided for low power idle periods.On-Chip Voltage Reference. The AD9763/AD9765/AD9767each include a 1.20 V temperature-compensated band gapvoltage reference.Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767each feature a flexible dual-port interface, allowing dual orinterleaved input data.ApplicationsCommunicationsBase stationsDigital synthesisQuadrature modulation3D ultrasound

The ADA4432-1 is a single-ended output fully integrated video reconstruction filter that combines overvoltage protection (short-to-battery [STB] protection) and short-to-ground (STG) protection on the outputs, with excellent video specifications and low power consumption. The combination of STB protection and robust ESD tolerance allows the ADA4432-1 to provide superior protection in the hostile automotive environment.The ADA4432-1 is a single-ended input/single-ended output video filter capable of driving long back-terminated cables.The short-to-battery protection integrated into the ADA4432-1 protects against both dc and transient overvoltage events, caused by an accidental short to a battery voltage up to 18 V. The Analog Devices, Inc., short-to-battery protection eliminates the need for large output coupling capacitors and other complicated circuits used to protect standard video amplifiers, saving space and cost.The ADA4432-1 features a high-order filter with ?3 dB cutoff frequency response at 10 MHz and 45 dB of rejection at 27 MHz. The ADA4432-1 features an internally fixed gain of 2 V/V. This makes the ADA4432-1 ideal for SD video applications, including NTSC and PAL.The ADA4432-1 operatea on single supplies as low as 2.6 V and as high as 3.6 V while providing the dynamic range required by the most demanding video systems.The ADA4432-1 is offered in an 8-lead, 3 mm ? 3 mm LFCSP package and a 6-lead SOT-23 package. It is rated for operation over the wide automotive temperature range of ?40?C to +125?C.Appplications Automotive rearview cameras Automotive video electronic control units (ECUs) Surveillance video systems

The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 ? on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs.The ADCLK954 features 12 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias Vcc to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK954 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

The ADL5373 supports a frequency of operation from 2300 MHzto 3000 MHz and is a pin-compatible member of the fixed gainquadrature modulator (F-MOD) family designed for use from300 MHz to 4000 MHz. The ADL5373 provides excellent phaseaccuracy and amplitude balance enabling high performanceintermediate frequency or direct radio frequency modulationfor communications systems.The ADL5373 provides a >500 MHz, 3 dB baseband bandwidth,making it ideally suited for use in broadband zero IF or lowIF-to-RF applications and in broadband digital predistortiontransmitters. The ADL5373 accepts two differential baseband inputs that aremixed with a local oscillator (LO) to generate a single-endedoutput.The ADL5373 is fabricated using the Analog Devices, Inc.advanced silicon-germanium bipolar process. It is availablein a 24-lead, exposed paddle, Pb-free LFCSP. Performance isspecified over a ?40?C to +85?C temperature range. A Pb-freeevaluation board is available.Applications WiMAX/broadband wireless access systems Satellite modems

The ADL5531 is a broadband, fixed-gain, linear amplifier that operates at frequencies up to 500 MHz. The device can be used in a wide variety of equipment, including cellular, satellite, broadband, and instrumentation equipment.The ADL5531 provides a gain of 20 dB, which is stable over frequency, temperature, power supply, and from device to device. This amplifier is single-ended and internally matched to 50 ?. Only input/output ac coupling capacitors, power supply decoupling capacitors, and external inductors are required for operation.The ADL5531 is fabricated on a GaAs HBT process and has an ESD rating of ?2 kV (Class 2). The device is packaged in an 8-lead 3 mm ? 3 mm LFCSP that uses an exposed paddle for excellent thermal impedance.The ADL5531 consumes 100 mA on a single 5 V supply and is fully specified for operation from ?40?C to +85?C.The dual-channel 20 dB gain version, ADL5534, is also available.

The ADM8611 /?ADM8612?/?ADM8613?/?ADM8614?/?ADM8615?are voltage supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. Apart from providing power-on reset signals, an on-chip watchdog timer can reset the microprocessor if it fails to strobe within a preset timeout period. A reset signal can also be asserted by an external push-button through a manual reset input.The ultralow power consumption of these devices makes them suitable for power efficiency sensitive systems, such as battery-powered portable devices and energy meters.The features of each member of the device family are shown in Table 9 in the data sheet. Each device subdivides into submodels with differences in factory preset voltage monitoring threshold options. In the range of 2 V to 4.63 V, 10 options are available for the ADM8611. In the range of 2.32 V to 4.63 V, five options are available for both the ADM8613 and ADM8614. A separate supply input allows the ADM8612 and ADM8615 to monitor 20 different low voltage levels from 0.5 V to 1.9 V. Not all device options are available as standard models.The ADM8611, ADM8612, ADM8613, and ADM8615 can reset on demand through the manual reset input. The watchdog function on the ADM8613, ADM8614, and ADM8615 monitors the heartbeat of the microprocessor through the WDI pin. The ADM8613 and ADM8614 have a watchdog disable input, which allows the user to disable the watchdog function, if required. The ADM8614 also has a watchdog timeout extension input, allowing the watchdog timeout to be extended from 1.6 sec to 100 sec.The ADM8611/ADM8612/ADM8613/ADM8614/ADM8615 are available in a 6-ball, 1.46 mm ? 0.96 mm WLCSP. These devices are specified over the temperature range of ?40?C to +85?C.??APPLICATIONS Portable/battery-operated equipment Microprocessor systems Energy metering Energy harvesting

The ADMV4928 is a silicon on insulator (SOI), 37.0 GHz to 43.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4928 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360? phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625? phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4928 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4928 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.The ADMV4928 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.The ADMV4928 comes in a compact, 239-ball, 10 mm ? 7 mm chip scale package ball grid array (CSP_BGA). The ADMV4928 operates over the ?40?C to +95?C case temperature (TC) range. This CSP_BGA package enables the ability to heatsink the ADMV4928 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).APPLICATIONSmmW 5G applicationBroadband communication