The SSM4321 is a fully integrated, high efficiency, Class-Daudio amplifier with digitized output of output voltage, outputcurrent, and the PVDD supply voltage. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a 2.5 V to 5.5 V supply for the amplifier and a 1.42 V to 3.6 V supply for input/output. The SSM4321 is capable of delivering 2.2 W of continuous output power with 100 dB.The SSM4321 includes circuitry to sense output current, output voltage, and the PVDD supply voltage. Current sense is performedusing an external sense resistor that is connected between anoutput pin and the load. The output current and voltage are sentto ADCs with 16-bit resolution; the PVDD supply voltage is sent to an ADC with 8-bit resolution.The outputs of these ADCs are available on the TDM or I2S output serial port. The SLOT pin is used to determine which of four possible output slots is used on the TDM interface. A stereo I2S interface can be selected by reversing the pin connections forBCLK and FSYNC. Also, a direct PDM bit stream of voltage andcurrent data can be selected via the SLOT pin.Spread-spectrum pulse density modulation (PDM) is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The inherent randomized nature of spread-spectrum PDM eliminates the clock intermodulation (beating effect) of several amplifiers in close proximity.The SSM4321 produces ultralow EMI emissions that significantlyreduce the radiated emissions at the Class-D outputs, particularly above 100 MHz. The ultralow EMI emissions of the SSM4321 arealso helpful for antenna and RF sensitivity problems.The device includes a highly flexible gain select pin that requiresonly one series resistor to select a gain setting of 0 dB, 3 dB, 6 dB, 9 dB, or 12 dB. Input impedance is fixed at 80 k?, independent of the selected gain.The SSM4321 has a shutdown mode with a typical shutdowncurrent of

The AD725 is a very low cost general purpose RGB to NTSC/PAL encoder that converts red, green and blue color componentsignals into their corresponding luminance (basebandamplitude) and chrominance (subcarrier amplitude and phase)signals in accordance with either NTSC or PAL standards.These two outputs are also combined on-chip to provide acomposite video output. All three outputs are available separatelyat voltages of twice the standard signal levels as requiredfor driving 75 ?, reverse-terminated cables.An evaluation board is available for this product and may be ordered using the following product number: AD725-EB.

Demonstration circuit DC1154 is a Telecom non isolated DC/DC converter featuring the LTC3873 constant frequency current mode flyback controller. The DC1154 converts 36V to 72V input voltage to an isolated 3A of output current at 3.3V. The 200kHz constant frequency operation is maintained down to very light load to reduce low frequency noise generated over a wide range of load current. The DC1154 also provides an isolated design by installing the optocoupler and LTC4430 related circuitry. The demonstration circuit can be easily modified to generate different output voltages up to 15V. As output voltage is increased, the maximum output current must be reduced to limit the output power to no more than 10W.

The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332 / AD8334 / AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4? local oscillator (LO) input that divides this signal and generates the necessary 0? and 90? phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input.Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5? phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45?, then the user can phase align Channel 2 with Channel 1 by choosing the correct code.The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021?or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665?(16-bit, 570 kSPS).An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again.The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers

The LTC3830/LTC3830-1 are high power, high efficiency switching regulator controllers optimized for 3.3V-5V to 1.xV-3.xV step-down applications. A precision internal reference and feedback system provide ?1% output regulation over temperature, load current and line voltage variations. The LTC3830/LTC3830-1 use a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel FET, providing an adjustable current limit without a current sense resistor.The LTC3830/LTC3830-1 operate with an input supply voltage as low as 3V and with a maximum duty cycle of >91% over temperature. They include a fixed frequency PWM oscillator for low output ripple operation. The 200kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to 500kHz. In shutdown mode, the LTC3830 supply current drops to

DC1767A: Demo Board for the LTC2997 Remote/Internal Temperature Sensor.

The LTC2377-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2377-16 has a ?VREF fully differential input range with VREF ranging from 2.5V to 5.1V. The LTC2377-16 consumes only 6.8mW and achieves ?0.5LSB INL maximum, no missing codes at 16 bits with 97dB SNR.The LTC2377-16 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 500ksps throughput with no cycle latency makes the LTC2377-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2377-16 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate.The LTC2377-16 features a unique digital gain compression (DGC) function, which eliminates the driver amplifier?s negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling function that maps zero-scale code from 0V to 0.1 ? VREF and full-scale code from VREF to 0.9 ? VREF. For a typical reference voltage of 5V, the full-scale input range is now 0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply.Applications Medical Imaging High Speed Data Acquisition Portable or Compact Instrumentation Industrial Process Control Low Power Battery-Operated Instrumentation ATE

Demonstration circuit 1801A is a dual output 1.5V/20A and 1.2V/20A synchronous buck converter operating with a switching frequency of 300kHz over an input voltage range of 4.5V to 14V. The demo board comes in two versions. The A version uses inductor DCR current sensing for high efficiency. The B version uses 2mΩ sense resistor for accurate current sensing with a low DCR ferrite inductor. The fixed on-time valley current mode topology of the LTC3838 allows for a fast load step response.

The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con-verter (ADC) with an on-chip sample-and-hold circuit designedfor low cost, low power, small size, and ease of use. The productoperates at a conversion rate of up to 65 MSPS and is optimized foroutstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 94 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). ApplicationsMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD8129/AD8130 are designed as receivers for the transmission of high speed signals over twisted-pair cables to work with the AD8131 or AD8132 drivers. Either can be used for analog ordigital video signals and for high speed data transmission.The AD8129/AD8130 are differential-to-single-ended amplifiers with extremely high CMRR at high frequency. Therefore, they canalso be effectively used as high speed instrumentation amps or for converting differential signals to single-ended signals.

Reaching speeds of up to 1 GHz, the ADSP-2159x processors are members of the SHARC? family of products. The ADSP-2159x processor is a dual-SHARC+? core DSP that doubles the audio performance of its single-SHARC+ core ADSP-2156x predecessor while maintaining pin-compatibility to it in the BGA package, providing design scalability from 400 MHz (ADSP-21566) to 2 GHz (ADSP-21593).The ADSP-2159x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.APPLICATIONS Automotive: audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS Consumer & Professional Audio: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

The AD9121 is a dual, 14-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9121 TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9121 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (IF). Proprietary DAC output switching technique enhances dynamic performance. Current outputs are easily configured for various single-ended or differential circuit topologies. Flexible LVDS digital interface allows the standard 28-wire bus to be reduced to one-half of the width.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

The SSM2375 is a fully integrated, high efficiency, Class-D audioamplifier. It is designed to maximize performance for mobilephone applications. The application circuit requires a minimumof external components and operates from a single 2.5 V to 5.5 Vsupply. It is capable of delivering 3 W of continuous output powerwith 100 dB.Spread-spectrum pulse density modulation (PDM) is used toprovide lower EMI-radiated emissions compared with otherClass-D architectures. The inherent randomized nature ofspread-spectrum PDM eliminates the clock intermodulation(beating effect) of several amplifiers in close proximity.The SSM2375 includes an optional modulation select pin(ultralow EMI emissions mode) that significantly reduces theradiated emissions at the Class-D outputs, particularly above100 MHz. In ultralow EMI emissions mode, the SSM2375can pass FCC Class B radiated emission testing with 50 cm,unshielded speaker cable without any external filtering.The device also includes a highly flexible gain select pin thatallows the user to select a gain of 0 dB, 3 dB, 6 dB, 9 dB, or12 dB. The gain selection feature improves gain matchingbetween multiple SSM2375 devices within a single applicationas compared to using external resistors to set the gain.The SSM2375 has a micropower shutdown mode with a typicalshutdown current of 20 nA. Shutdown is enabled by applyinga logic low to the SD pin.The device also includes pop-and-click suppression circuitry.This suppression circuitry minimizes voltage glitches at theoutput during turn-on and turn-off, reducing audible noiseon activation and deactivation.Other features that simplify system-level integration of theSSM2375 include input low-pass filtering to suppress out-of-bandDAC noise interference to the PDM modulator and fixed-inputimpedance to simplify component selection across multipleplatform production builds.The SSM2375 is specified over the industrial temperature rangeof ?40?C to +85?C. It has built-in thermal shutdown and outputshort-circuit protection. It is available in a halide-free, 9-ball,1.5 mm ? 1.5 mm wafer level chip scale package (WLCSP).Applications Mobile phones MP3 players Portable electronics

The LTM8049 is a Dual SEPIC/Inverting ?Module? (power module) DC/DC Converter. Each of the two outputs can be easily configured as a SEPIC or Inverting converter by simply grounding the appropriate output rail. The LTM8049 includes power devices, inductors, control circuitry and passive components. All that is needed to complete the design are input and output caps, and small resistors to set the output voltages and switching frequency. Other components may be used to control the soft-start and undervoltage lockout.The LTM8049 is packaged in a thermally enhanced, compact (15mm ? 9mm) over-molded Ball Grid Array (BGA) package suitable for automated assembly by standard surface mount equipment. The LTM8049 is RoHS compliant.Applications Battery Powered Regulator Local Negative Voltage Regulator Low Noise Amplifier Power

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz.?The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package.?The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.?Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution.?Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution.?With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures.?Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.?Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins.?The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.?The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers?3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The AD9231 is a monolithic, dual-channel, 1.8 V supply, 12-bit, 20 MSPS / 40?MSPS / 65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.The AD9231 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS The AD9231 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9231 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.?APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

DC1796A-D Demo Board for: LTC6360 Very Low Noise Single-Ended SAR ADC Driver with True Zero Output LTC2364-16 16-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR

The AD8341 vector modulator performs arbitrary amplitudeand phase modulation of an RF signal. Because the RF signalpath is linear, the original modulation is preserved. This part canbe used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be controlledfrom a maximum of ?4.5 dB to less than ?34.5 dB, and the phasecan be shifted continuously over the entire 360? range. For maximumgain, the AD8341 delivers an OP1dB of 8.5 dBm, an OIP3of 17.5 dBm, and an output noise floor of ?150.5 dBm/Hz,independent of phase. It operates over a frequency range of1.5 GHz to 2.4 GHz.The baseband inputs in Cartesian I and Q format control theamplitude and phase modulation imposed on the RF inputsignal. Both I and Q inputs are dc-coupled with a ?500 mVdifferential full-scale range. The maximum modulationbandwidth is 230 MHz, which can be reduced by adding externalcapacitors to limit the noise bandwidth on the control lines.Both the RF inputs and outputs can be used differentially orsingle-ended and must be ac-coupled. The RF input and outputimpedances are nominally 50 ? over the operating frequencyrange. The DSOP pin allows the output stage to be disabledquickly in order to protect subsequent stages from overdrive.The AD8341 operates off supply voltages from 4.75 V to 5.25 Vwhile consuming approximately 125 mA.The AD8341 is fabricated on Analog Devices? proprietary, highperformance 25 GHz SOI complementary bipolar IC process. Itis available in a 24-lead, lead-free LFCSP package and operatesover a ?40?C to +85?C temperature range. Evaluation boardsare available. Applications RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, WCDMA, GSM/EDGE linear power amplifiers Smart antennasAvailabilitySamples part number AD8341ACP and an evaluation board, part number AD8341-EVAL, are available.Companion ProductsAD8302 - LF - 2.7GHz RF/IF Gain Phase DetectorAD8340 - RF Vector Modulator 700MHz to 1000MHzOther Modulator / Demodulator ProductsAD8345 - 250MHz to 1000MHz Low Noise RF/IF ModulatorAD8346 - 800MHz to 2.5GHz Lower Power Direct Up-Conversion ModulatorAD8347 - 800MHz to 2.7GHz Direct Conversion DemodulatorAD8348 - 50MHz to 1000MHz RF/IF Quadrature DemodulatorAD8349 - 700MHz - 2.7GHz Low Noise Direct Up Conversion Modulator

The AD737 is a low power, precision, monolithic, true rms-to-dc converter. It is laser trimmed to provide a maximum error of ?0.2 mV ? 0.3% of reading with sine wave inputs. Furthermore, it maintains high accuracy while measuring a wide range of input waveforms, including variable duty cycle pulses and triac (phase) controlled sine waves. The low cost and small physical size of this converter make it suitable for upgrading the performance of non-rms precision rectifiers in many applications. Compared to these circuits, the AD737 offers higher accuracy at equal or lower cost.The AD737 computes the rms value of both the ac and dc input voltages, and is ac-coupled by adding an input capacitor. In this mode, the AD737 can resolve input signal levels of 100 ?V rms or less, despite variations in temperature or supply voltage. High accuracy is maintained for input waveforms with crest factors of 1 to 3 and crest factors at 2.5% or less with respect to full-scale input level.The AD737 has no output buffer amplifier, thereby significantly reducing dc offset errors occurring at the output, which makes the device highly compatible with high input impedance ADCs.Requiring only 160 ?A of power supply current, the AD737 is optimized for use in portable multimeters and other battery-powered applications. In power-down mode, the standby supply current in is typically 25 ?A.The AD737 has both high (1012 ?) and low impedance input options. The high-Z FET input connects high source impedance input attenuators, and a low impedance (8 k?) input accepts rms voltages of up to 0.9 V while operating from the minimum power supply voltage of ?2.5 V. The two inputs can be used either single ended or differentially.The AD737 achieves 1% of reading error bandwidth, exceeding 10 kHz for input amplitudes from 20 mV rms to 200 mV rms, while consuming only 0.72 mW.The AD737 is available in two performance grades. The AD737J and AD737K grades operate over the commercial temperature range of 0?C to 70?C. The AD737JR-5 is tested with supply voltages of ?2.5 V dc. The AD737A grade operates over the industrial temperature range of ?40?C to +85?C. The AD737 is available in two low cost, 8-lead packages: PDIP and SOIC_N.PRODUCT HIGHLIGHTS Computes average rectified, absolute, or true rms value of a signal regardless of waveform. Only one external component, an averaging capacitor, is required for the AD737 to perform true rms measurement. The standby power consumption of 125 ?W makes the AD737 suitable for battery-powered applications.

Demonstration circuit 486B is a dual Smart Battery PowerPath and charger controller featuring the LTC1760. The input voltage is 12 to 20V. The charger output voltage is programmed SMBus serial interface. The maximum charge current is 4A. The demo board has been optimized to work with 2, 3 and 4- Cell Li-ion battery packs. A jumper is provided to select trip for low battery voltage (LOBAT), VLIMIT (VLIM), and ILIMIT (ILIM). The LTC1760 follows the Smart Battery Standards for the Smart Battery System Manager (SBSM) specification.