The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. External reference or driver components are not required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported.The AD9655 typically consumes less than 2 mW in SPI powerdown mode. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9655 is available in a RoHS-compliant, 32-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C. This device is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Two ADCs are contained in a small, spacesaving package. Pin compatible to the AD9645 14-bit and AD9635 12-bit dual ADCs. Ease of use. A DCO operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand held scope meters Portable medical imaging Radar/LIDAR

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9704/AD9705/AD9706/AD9707?are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI?) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTS Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC?converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference. Industry-Standard 32-Lead LFCSP Package.

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.The AD9737A/AD9739A are manufactured on a 0.18 ?m CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mixmode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics

The AD9743/AD9745/AD976/AD9747 are pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 10-/12-/14-/16-bit resolutions and sample rates of up to 250 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators, such as the ADL5370.A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency.A serial peripheral interface (SPI) port provides full programmability. In addition, some pin-programmable features are offered for those applications without a controller.PRODUCT HIGHLIGHTS Low noise and intermodulation distortion (IMD) enables high quality synthesis of wideband signals. Proprietary switching output for enhanced dynamic performance. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements.APPLICATIONS Wireless infrastructure: W-CDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications: LMDS/MMDS, point-to-point Instrumentation: Radio Frequency (RF) signal generators, arbitrary waveform generators

The AD9764 is the 14-bit resolution member of the TxDAC?series of high performance, low power CMOS digital-to-analogconverters (DACs). The TxDAC?; family, which consists of pincompatible 8-, 10-, 12-, and 14-bit DACs, is specificallyoptimized for the transmit signal path of communicationsystems. All of the devices share the same interface options,small outline package and pinout, providing an upward ordownward component selection path based on performance,resolution and cost. The AD9764 offers exceptional ac and dcperformance while supporting update rates up to 125 MSPS.The AD9764?s flexible single-supply operating range of 2.7 V to5.5 V and low power dissipation are well suited for portable andlow power applications. Its power dissipation can be furtherreduced to a mere 45 mW with a slight degradation in performanceby lowering the full-scale current output. Also, a power-downmode reduces the standby power dissipation to approximately25?mW.The AD9764 is manufactured on an advanced CMOS process.A segmented current source architecture is combined with aproprietary switching technique to reduce spurious componentsand enhance dynamic performance. Edge-triggered inputlatches and a 1.2 V temperature compensated bandgap referencehave been integrated to provide a complete monolithicDAC solution. Flexible supply options support +3 V and +5 VCMOS logic families.The AD9764 is a current-output DAC with a nominal full-scaleoutput current of 20 mA and >100 k? output impedance.Differential current outputs are provided to support single-endedor differential applications. Matching between the twocurrent outputs ensures enhanced dynamic performance in adifferential output configuration. The current outputs may betied directly to an output resistor to provide two complementary,single-ended voltage outputs or fed directly into a transformer.The output voltage compliance range is 1.25 V.The on-chip reference and control amplifier are configured formaximum accuracy and flexibility. The AD9764 can be drivenby the on-chip reference or by a variety of external referencevoltages. The internal control amplifier, which provides a wide(>10:1) adjustment span, allows the AD9764 full-scale currentto be adjusted over a 2 mA to 20 mA range while maintainingexcellent dynamic performance. Thus, the AD9764 may operateat reduced power levels or be adjusted over a 20 dB range toprovide additional gain ranging capabilities.The AD9764 is available in a 28-lead SOIC package. It isspecified for operation over the industrial temperature range.Product Highlights The AD9764 is a member of the TxDAC product family that provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. Manufactured on a CMOS process, the AD9764 uses a proprietary switching technique that enhances dynamic performance beyond that previously attainable by higher power/cost bipolar or BiCMOS devices. On-chip, edge-triggered input CMOS latches readily interface to +3 V and +5 V CMOS logic families. The AD9764 can support update rates up to 125 MSPS. A flexible single-supply operating range of 2.7 V to 5.5 V, and a wide full-scale current adjustment span of 2 mA to 20 mA, allows the AD9764 to operate at reduced power levels. The current output(s) of the AD9764 can be easily configured for various single-ended or differential circuit topologies.Applications Communication Transmit Channel: - Basestations - ADSL/HFC Modems Instrumentation

The AD9763/AD9765/AD9767 are dual-port, high speed, 2-channel, 10-/12-/14-bit CMOS DACs. Each part integratestwo high quality TxDAC+? cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/AD9765/AD9767 offer exceptional ac and dc performancewhile supporting update rates of up to 125 MSPS.The AD9763/AD9765/AD9767 have been optimized forprocessing I and Q data in communications applications. Thedigital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.A mode control pin allows the AD9763/AD9765/AD9767 to interface to two separate data ports, or to a single interleavedhigh speed data port. In interleaving mode, the input datastream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACsand updated at half the input data rate.The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See theGain Control Mode section for important date codeinformation on this feature.The DACs utilize a segmented current source architecturecombined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC providesdifferential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide anominal full-scale current of 20 mA. The full-scale currentsbetween each DAC are matched to within 0.1%.The AD9763/AD9765/AD9767 are manufactured on anadvanced, low cost CMOS process. They operate from a singlesupply of 3.3 V to 5 V and consume 380 mW of power.Product HighlightsThe AD9763/AD9765/AD9767 are members of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information.Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%.Low Power. Complete CMOS dual DAC function operates on 380 mW from a 3.3 V to 5 V single supply. The DAC full-scalecurrent can be reduced for lower power operation, and a sleepmode is provided for low power idle periods.On-Chip Voltage Reference. The AD9763/AD9765/AD9767each include a 1.20 V temperature-compensated band gapvoltage reference.Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767each feature a flexible dual-port interface, allowing dual orinterleaved input data.ApplicationsCommunicationsBase stationsDigital synthesisQuadrature modulation3D ultrasound

The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,high dynamic range TxDAC? devices, respectively, that providea sample rate of 800 MSPS, permitting multicarrier generationup to the Nyquist frequency. Features are included for optimizingdirect conversion transmit applications, including complexdigital modulation, as well as gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlesslywith analog quadrature modulators, such as the ADL5375family from Analog Devices, Inc. A serial peripheral interface(SPI) provides for programming and readback of many internalparameters. Full-scale output current can be programmed overa range of 10 mA to 30 mA. The AD9785/AD9787/AD9788family is manufactured on a 0.18 ?m CMOS process and operatesfrom 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFPpackage.Product Highlights Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. Proprietary DAC output switching technique enhances dynamic performance. CMOS data input interface with adjustable setup and hold. Low power complex 32-bit numerically controlled oscillators (NCOs).Applications Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM Digital high or low IF synthesis Transmit diversity Wideband communications LMDS/MMDS, point-to-point

The AD9914 is a direct digital synthesizer (DDS) featuring a 12?bit DAC. The AD9914 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 1.4 GHz. The AD9914 enables fast frequency hopping and fine tuning resolution (64?bit capable using programmable modulus mode). The AD9914 also offers fast phase and amplitude hopping capability. The frequency tuning and control words are loaded into the AD9914 via a serial or parallel input/output port.The AD9914 also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase, or amplitude. A high speed, 32-bit parallel data input port is included, enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency, and amplitude tuning words.The AD9914 is specified to operate over the extended industrial temperature range (see the Absolute Maximum Ratings section in the data sheet).APPLICATIONS Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping

The AD9954 is a direct digital synthesizer (DDS) that uses advanced technology, coupled with an internal high speed, high performance DAC to form a complete, digitally programmable, high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 160 MHz. The AD9954 enables fast frequency hopping coupled with fine tuning of both frequency (0.01 Hz or better) and phase (0.022? granularity).The AD9954 is programmed via a high speed serial I/O port. The device includes static RAM to support flexible frequency sweep capability in several modes, plus a user-defined linear sweep mode of operation. Also included is an on-chip high speed comparator for applications requiring a square wave output. An on-chip oscillator and PLL circuitry provide users with multiple approaches to generate the device?s system clock.The AD9954 is specified to operate over the extended industrial temperature range.Applications Agile LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers

The AD9958 consists of two DDS cores that provide independentfrequency, phase, and amplitude control on each channel.This flexibility can be used to correct imbalances betweensignals due to analog processing, such as filtering, amplification,or PCB layout related mismatches. Because both channels sharea common system clock, they are inherently synchronized.Synchronization of multiple devices is supported.The AD9958 can perform up to a 16-level modulation offrequency, phase, or amplitude (FSK, PSK, ASK). Modulation isperformed by applying data to the profile pins. In addition, theAD9958 also supports linear sweep of frequency, phase, oramplitude for applications such as radar and instrumentation.The AD9958 serial I/O port offers multiple configurations toprovide significant flexibility. The serial I/O port offers an SPIcompatiblemode of operation that is virtually identical to theSPI operation found in earlier Analog Devices, Inc., DDSproducts. Flexibility is provided by four data pins (SDIO_0 /SDIO_1 / SDIO_2 / SDIO_3) that allow four programmablemodes of serial I/O operation.The AD9958 uses advanced DDS technology that provides lowpower dissipation with high performance. The device incorporatestwo integrated, high speed 10-bit DACs with excellent widebandand narrow-band SFDR. Each channel has a dedicated 32-bitfrequency tuning word, 14 bits of phase offset, and a 10-bitoutput scale multiplier.The DAC outputs are supply referenced and must be terminatedinto AVDD by a resistor or an AVDD center-tappedtransformer. Each DAC has its own programmable reference toenable different full-scale currents for each channel.The DDS acts as a high resolution frequency divider with theREFCLK as the input and the DAC providing the output. TheREFCLK input source is common to both channels and can bedriven directly or used in combination with an integratedREFCLK multiplier (PLL) up to a maximum of 500 MSPS. ThePLL multiplication factor is programmable from 4 to 20, ininteger steps. The REFCLK input also features an oscillatorcircuit to support an external crystal as the REFCLK source.The crystal must be between 20 MHz and 30 MHz. The crystalcan be used in combination with the REFCLK multiplier.The AD9958 comes in a space-saving 56-lead LFCSP package.The DDS core (AVDD and DVDD pins) is powered by a 1.8 Vsupply. The digital I/O interface (SPI) operates at 3.3 V andrequires the pin labeled DVDD_I/O (Pin 49) be connectedto 3.3 V.The AD9958 operates over the industrial temperature range of?40?C to +85?C.Applications Agile local oscillators Phased array radars/sonars Instrumentation Synchronized clocking RF source for AOTF Single-side band suppressed carriers Quadrature communications

The AD9993 is a mixed-signal front-end (MxFE?) device that integrates four 14-bit ADCs and two 14-bit DACs. Figure 1 shows the block diagram of the MxFE. The MxFE is programmable using registers accessed via a serial peripheral interface (SPI). ADC and DAC datapaths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks.The MxFE DACs are part of the Analog Devices, Inc., high speed CMOS DAC core family. These DACs are designed to be used in wide bandwidth communication system transmitter (Tx) signal chains.The MxFE ADCs are multistage pipelined CMOS ADC cores designed for use in communications receivers.APPLICATIONSPoint to point microwave backhaul radioWireless repeaters

The ADA2200 is a synchronous demodulator and configurable analog filter designed to perform precision magnitude and phase measurements in low power, sensor signal conditioning and data acquisition applications for the industrial, medical, and communications markets. Implemented with ADI?s patent pending sampled analog technology (SAT), the ADA2200 is an analog input, sampled analog output device that includes an analog domain, low-pass 1/8x decimation finite impulse response (FIR) filter, a configurable infinite impulse response (IIR) filter, mixer with 0?/90? phase selection, reference clock and ADC driver output. Utilizing sampled analog technology, the signal processing is performed entirely in the analog domain by charge sharing among capacitors, which eliminates the effects of quantization noise and rounding errors and reduces downstream ADC sample rates while also offloading computationally heavy tasks from the digital processor or micro-controller.The ADA2200 acts as a precision filter when the demodulation function is disabled. The filter has a programmable bandwidth and tunable center frequency. The filter characteristics are highly stable over temperature, supply, and process variation.Single-ended and differential signal interfaces are possible on both input and output terminals, simplifying the connection to other components of the signal chain. The low power consumption and rail-to-rail operation is ideal for battery-powered and low voltage systems.The ADA2200 can be programmed over its SPI-compatible serial port or can automatically boot from the EEPROM through its I2C interface. On-chip clock generation produces a mixing signal with a programmable frequency and phase. In addition, the ADA2200 synchronization output signal eases interfacing to other sampled systems, such as data converters and multiplexers.The ADA2200 is available in a 16-lead TSSOP package. Its performance is specified over the industrial temperature range of ?40?C to +85?C. Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant.Applications Synchronous demodulation Sensor signal conditioning Lock-in amplifiers Phase detectors Precision tunable Filters Signal recovery Control systems

The ADA4530-1 is a femtoampere (10?15 A) level input bias current operational amplifier suitable for use as an electrometer that also includes an integrated guard buffer. It has an operating voltage range of 4.5 V to 16 V, enabling it to operate in conventional 5 V and 10 V single supply systems as well as ?2.5 V and ?5 V dual supply systems.It provides ultralow input bias currents that are production tested at 25?C and at 125?C to ensure the device meets its performance goals in user systems. The integrated guard buffer isolates the input pins from leakage in the printed circuit board (PCB), minimizes board component count, and enables easy system design. The ADA4530-1 is available in an industry-standard surface-mount 8-lead SOIC package with a unique pinout optimized to prevent signals from coupling between the sensitive input pins, the power supplies, and the output pin while enabling easy routing of the guard ring traces.The ADA4530-1 also offers low offset voltage, low offset drift, and low voltage and current noise needed for the types of applications that require such low leakages.To maximize the dynamic range of the system, the ADA4530-1 has a rail-to-rail output stage that can typically drive to within 30 mV of the supply rails under a 10 k? load.The ADA4530-1 operates over the ?40?C to +125?C industrial temperature range and is available in an 8-lead SOIC package.Applications Laboratory and analytical instrumentation: spectrophotometers, chromatographs, mass spectrometers, and potentiostatic and amperostatic coulometry Instrumentation: picoammeters and coulombmeters Transimpedance amplifier (TIA) for photodiodes, ion chambers, and working electrode measurements High impedance buffering for chemical sensors and capacitive sensors

The ADA4806-1 is a high speed, voltage feedback, rail-to-rail output, single operational amplifier with three power modes: full power mode, sleep mode, and shutdown mode. In full power mode, this amplifier provides a wide bandwidth of 105 MHz at a gain of +1, a fast slew rate 160 V/?s, and excellent dc precision with a low input offset voltage of 125 ?V (maximum) and an input offset voltage drift of 1.5 ?V/?C (maximum), while consuming only 500 ?A of quiescent current. Despite being a low power amplifier, the ADA4806-1 provides excellent overall performance, making it ideal for low power, high resolution data conversion systems.For data conversion applications where minimizing power dissipation is paramount, the ADA4806-1 offers a method to reduce power by dynamically scaling the quiescent power of the ADC driver with the sampling rate of the system by switching the amplifier to a lower power mode between samples.Sleep mode reduces the amplifier quiescent current to 74 ?A and provides a fast turn-on time of only 0.45 ?s, enabling the use of dynamic power scaling for sample rates approaching 2 MSPS. For additional power savings at lower samples rates, the shutdown mode further reduces the quiescent current to only 2.9 ?A.The ADA4806-1 operates over a wide range of supply voltages and is fully specified at supplies of 3 V, 5 V and ?5 V. This amplifier is available in a compact, 8-lead SOT-23 package and is rated to operate over the industrial temperature range of ?40?C to +125?C.Applications Portable and battery-powered instruments and systems High channel density data acquisition systems Precision analog-to-digital converter (ADC) drivers Voltage reference buffers Portable point of sales terminals Active RFID readers

The ADA4853-1/ADA4853-2/ADA4853-3 are low power, low cost, high speed, rail-to-rail output op amps with ultralow power disables that are ideal for portable consumer electronics. Despite their low price, the ADA4853-1/ADA4853-2/ADA4853-3 provide excellent overall performance and versatility. The 100 MHz, ?3 dB bandwidth, and 120 V/?s slew rate make these amplifiers well-suited for many general-purpose, high speed applications.The ADA4853-1/ADA4853-2/ADA4853-3 voltage feedback op amps are designed to operate at supply voltages as low as 2.65 V and up to 5 V using only 1.4 mA of supply current per amplifier. To further reduce power consumption, the amplifiers are equipped with a power-down mode that lowers the supply current to less than 1.5 ?A maximum, making them ideal in battery-powered applications.The ADA4853-1/ADA4853-2/ADA4853-3 provide users with a true single-supply capability, allowing input signals to extend 200 mV below the negative rail and to within 1.2 V of the positive rail. On the output, the amplifiers can swing within 200 mV of either supply rail.With their combination of low price, excellent differential gain (0.2%), differential phase (0.10?), and 0.5 dB flatness out to 22 MHz, these amplifiers are ideal for video applications.The ADA4853-1 is available in a 6-lead SC70, the ADA4853-2 is available in a 16-lead LFCSP_WQ, and the ADA4853-3 is available in both a 16-lead LFCSP_WQ and a 14-lead TSSOP. The ADA4853-1 temperature range is ?40?C to +85?C while the ADA4853-2/ADA4853-3 temperature range is ?40?C to +105?C. Applications Automotive infotainment systems Automotive safety systems Portable multimedia players Video cameras Digital still cameras Consumer video Clock buffer

The ADA4859-3 (triple) is a single-supply, high speed current feedback amplifier with an integrated charge pump that eliminates the need for negative supplies in order to output negative voltages or output a 0 V level for video applications. The 195 MHz, large signal ?3 dB bandwidth at a fixed gain of 2, as well as the 740 V/?s slew rate, make this amplifier ideal for high resolution professional and consumer video applications. The amplifier also has a wide input common-mode voltage range that extends from 1.8 V below ground to 1.2 V below the positive rail at 5 V supply.This triple video amplifier is designed to operate on supply voltages of 3.3 V to 5 V, using only 38 mA total quiescent current, including the charge pump. To further reduce the power consumption, it is equipped with a power-down feature that lowers the total supply current to as low as 2 mA when the amplifier is not being used. Even in power-down mode, the charge pump can be used to power external components. The maximum output current for external use is 50 mA at ?3 V.The ADA4858-3 is available in a 16-lead LFCSP, and it is designed to work over the industrial temperature range of ?40?C to +105?C.ApplicationsProfessional videoConsumer videoImagingActive filtersData Sheet, Rev. 0, 11/2008