The ADRF5160 is a silicon-based, high power, 0.7 GHz to 4.0 GHz, silicon, single-pole, double-throw (SPDT) reflective switch in a leadless, surface-mount package. The switch is ideal for high power and cellular infrastructure applications, such as long-term evolution (LTE) base stations. The ADRF5160 has high power handling of 41 dBm (8 dB PAR LTE, long-term (>10 years) average typical), a low insertion loss of 0.7 dB typical to 2.0 GHz, an input third-order intercept (IP3) of 70 dBm (typical), and a 0.1 dB compression point (P0.1dB) of 47 dBm. On-chip circuitry operates at a single positive supply voltage of 5 V at a typical supply current of 1.1 mA, making the ADRF5160 an ideal alternative to pin diode-based switches. The ADRF5160 comes in a RoHS compliant, compact 32-lead, 5 mm ? 5 mm LFCSP.Applications Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement

The ADRF5519 is a dual-channel, integrated RF, front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.3 GHz to 2.8 GHz. The ADRF5519 is configured in dual channels with a cascading two stage low noise amplifier (LNA) and a high power silicon single pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.0 dB and a high gain of 35 dB at 2.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 14 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, RF inputs are connected to a termination pin (ANT-CHA or ANT-CHB connected to TERM-CHA or TERM-CHB, respectively). The switch provides a low insertion loss of 0.5 dB and handles a long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The device comes in a RoHS-compliant, compact, 6 mm ? 6 mm, 40-lead LFCSP package.APPLICATIONSWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems

The ADRF5545A is a dual-channel, integrated radio frequency (RF), front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.4 GHz to 4.2 GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (

The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps.This device operates from 9 kHz to 40 GHz with better than 4.5 dB of insertion loss and excellent attenuation accuracy. The ATTIN port of the ADRF5720 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states.The ADRF5720 requires a dual supply voltage of +3.3 V and ?3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5720 is pin-compatible with the ADRF5730, the fast switching version, which operates from 100 MHz to 40 GHz.The ADRF5720 RF ports are designed to match a characteristic impedance of 50 ?. For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristicssection, and the Applications Information section for more details.The ADRF5720 comes in a 24-terminal, 4 mm ? 4 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5740 is a silicon, 4-bit digital attenuator with 22 dB attenuation control range in 2 dB steps.The ADRF5740 operates from 10 MHz to 60 GHz with less than 3.3 dB of insertion loss and with ?(0.2 + 7.0% of attenuation state) of attenuation accuracy at 55 GHz. The ATTIN port of the ADRF5740 has an RF input power handling capability of 24 dBm average and 24 dBm peak for all states.The ADRF5740 requires a dual supply voltage of +3.3 V and ?3.3 V. The ADRF5740 features parallel mode control, and CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5740 RF ports are designed to match a characteristic impedance of 50 ?. The ADRF5740 comes in a 16-terminal, 2.5 mm ? 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells? FDD and TDD active antenna systems? Microwave, nonline of sight (NLOS) backhaul systems

The ADUX1020 is a highly efficient photometric sensor with an integrated 14-bit analog-to-digital converter (ADC) and a 20-bit burst accumulator that works in concert with a flexible light emitting diode (LED) driver. It is designed to modulate a LED and measure the corresponding optical return signal. The digital engine includes circuitry and control for data aggregation and proximity detection.The data output and device configuration use a 1.8 V I2C interface. The control circuitry includes flexible LED pulse width and period generation combined with synchronous detection. This circuitry is complemented by a low noise, low power, and wide dynamic range configurable analog front end (AFE), clock generation, LED driver, and digital logic for position and smart sample mode (event driven x, y coordinates, relative z data). This complete AFE features ambient light rejection, avoiding corruption due to external interference.One inexpensive standard surface mount, broad angle or narrow angle IR LED (depending upon application) is required. This LED mounts externally to the ADUX1020.Packaged in a small clear mold 2 mm ? 3 mm, 8-lead LFCSP, the ADUX1020 is specified over an operating temperature range of ?40?C to +85?C.Applications Gesture for user interface (UI )control in portable devices Industrial/automation monitoring Presence detection Angle sensing

The ADV3200/ADV3201 are 32 ? 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching.The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The part is available in gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices.The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, Wavelet) Video conferencingData Sheet, Rev. 0, 11/2008

The ADV3202/ADV3203 are 32 ? 16 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input forac-coupled applications and a 2:1 on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolationat 5 MHz, the ADV3202/ADV3203 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3202/ADV3203 ideal for both composite and component video switching.The 16 independent output buffers of the ADV3202/ADV3203 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies can be used while consuming only 195 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, that can accommodate daisy chaining of several devices.The ADV3202/ADV3203 are packaged in a 176-lead exposed pad LQFP package (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals ?Composite video (NTSC, PAL, S, SECAM) ?RGB and component video routing ?Compressed video (MPEG, wavelet) Video conferencingData Sheet, Rev 0, 11/2008

ADZS-AD2428MINI is a low-cost, mini break-out board which can interface with EV-SOMCRR-EZKIT (via a 100-pin connector) or any custom board (via a 32 pin 0.1" header). It supports main and subordinate node capability as well as bus and local power configurations. An Automotive Audio Bus (A2B®) system consists of a single main node and at least one subordinate node, where the transceiver at the host controller is the main node. The main transceiver generates clock, synchronization, and framing for all subordinate nodes and is programmable over a control bus (I2C) for configuration and readback. An extension of this control bus is embedded in the A2B data stream, which enables the host to directly access subordinate transceiver registers and any I2C-connected peripherals on subordinate nodes. Transceivers can connect directly to PDM microphones and to numerous peripherals via I2C and a multichannel I2S/TDM interface. Finally, the transceiver also supports an A2B bus powering feature, where the main node supplies voltage and current to the subordinate nodes over the same daisy-chained, twisted pair wire cable as used for the communication link, thus eliminating the need for a power supply on bus-powered subordinate nodes. Due to the numerous configurations that are possible for a given A2B system, there are several evaluation platforms that can be used in combination to verify system operation, as summarized in the table below. Product Comparison Guide A2B Evaluation Board Main/Subordinate Power Supply I2S/TDM PDM Mics EVAL-AD2428WD1BZ Main/Subordinate Local Yes 3 EVAL-AD2428WB1BZ Subordinate Bus Yes 2 EVAL-AD2428WC1BZ Subordinate Bus No 4 EVAL-AD2428WG1BZ Subordinate Local Yes 0  ADZS-AD2428MINI  Main/Subordinate Local/Bus  Yes   0 Please contact your local ADI sales office or authorized ADI product distributor to receive additional product information and technical support.

The LTC1066-1 is an 8th order elliptic lowpass filter which simultaneously provides clock-tunability and DC accuracy. The unique and proprietary architecture of the filter allows 14 bits of DC gain linearity and a maximum of 1.5mV DC offset. An external RC is required for DC accurate operation. With ?7.5V supplies, a 20k resistor and a 1?F capacitor, the cutoff frequency can be tuned from 800Hz to 100kHz. A clock-tunable 10Hz to 100kHz operation can also be achieved (see Typical Application section).The filter does not require any external active components such as input/output buffers. The input/output impedance is 500M?/0.1? and the output of the filter can source or sink 40mA. When pin 8 is connected to V+ , the clock-to-cutoff frequency ratio is 50:1 and the input signal is sampled twice per clock cycle to lower the risk of aliasing. For frequencies up to 0.75fCUTOFF , the passband ripple is ?0.15dB. The gain at fCUTOFF is -1dB and the filter?s stopband attenuation is 80dB at 2.3fCUTOFF . Linear phase operation is also available with a clock-to-cutoff frequency ratio of 100:1 when pin 8 is connected to ground.The LTC1066-1 is available in an 18-pin SO Wide package..Applications Instrumentation Data Acquisition Systems Anti-Aliasing Filters Smoothing Filters Audio Signal Processing

The LT1372/LT1377 are monolithic high frequency switching regulators. They can be operated in all standard switching configurations including boost, buck, flyback, forward, inverting and 'Cuk.' A 1.5A high efficiency switch is included on the die, along with all oscillator, control and protection circuitry. All functions of the LT1372/LT1377 are integrated into 8-pin SO/PDIP packages.The LT1372/LT1377 typically consumes only 4mA quiescent current and has higher efficiency than previous parts. High frequency switching allows for very small inductors to be used. All surface mount components consume less than 0.5 square inch of board space.New design techniques increase flexibility and maintain ease of use. Switching is easily synchronized to an external logic level source. A logic low on the shutdown pin reduces supply current to 12?A. Unique error amplifier circuitry can regulate positive or negative output voltage while maintaining simple frequency compensation techniques. Nonlinear error amplifier transconductance reduces output overshoot on start-up or overload recovery. Oscillator frequency shifting protects external components during overload conditions.Applications Boost Regulators CCFL Backlight Driver Laptop Computer Supplies Multiple Output Flyback Supplies Inverting Supplies

The LTC1174 is a simple current mode DC/DC converter ideally suited for 9V to 5V, 5V to 3.3V or 5V to ?5V operation. With an internal 0.9? switch (at a supply voltage of 9V), the LTC1174 requires only four external components to construct a complete high efficiency DC/DC converter.Under a no load condition the LTC1174 draws only 130?A. In shutdown, it draws a mere 1?A making this converter ideal for current sensitive applications. In dropout, the internal P-channel MOSFET switch is turned on continuously allowing the user to maximize the life of the battery source.The maximum inductor current of the LTC1174 family is pin selectable to either 340mA or 600mA, optimizing efficiency for a wide range of applications. Operation up to 200kHz permits the use of small surface mount inductors and capacitors.For applications requiring higher output current or ultrahigh efficiency, see the LTC1148 data sheet.Applications Distributed Power Systems Step-Down Converters Inverting Converters Memory Backup Supply Portable Instruments Battery-Powered Equipment

The LTC1435 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using a fixed frequency architecture. Burst Mode? operation provides high efficiency at low load currents. A maximum duty cycle limit of 99% provides low dropout operation which extends operating time in battery-operated systems.The operating frequency is set by an external capacitor allowing maximum flexibility in optimizing efficiency. A secondary winding feedback control pin, SFB, guarantees regulation regardless of load on the main output by forcing continuous operation. Burst Mode operation is inhibited when the SFB pin is pulled low which reduces noise and RF interference.Soft start is provided by an external capacitor which can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum).For a guaranteed and test minimum on-time refer to the LTC1435A, the 'A' version of the LTC1435. The minimum on-time of the LTC1435A is guaranteed to be ?300ns. The only difference between these two parts is this guaranteed minimum on-time. Pricing is the same.Applications Notebook and Palmtop Computers, PDAs Cellular Telephones and Wireless Modems Portable Instruments Battery-Operated Devices DC Power Distribution Systems

The LTC2488 is a 4-channel (2-channel differential), 16-bit, No Latency ??? ADC with Easy Drive? technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2488 includes an integrated oscillator. This device can be configured to measure an external signal from combinations of 4 analog input channels operating in single ended or differential modes. It automatically rejects line frequencies of 50Hz and 60Hz simultaneously. The LTC2488 allows a wide common mode, input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion after a new channel selection is valid.Applications Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control

DC1011A-B: Demo Board for the LTC2496 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation.

DC1015A - Demo Board for: LTC3602 - 2.5A, 10V, Monolithic Synchronous Step-Down Regulator

DC1019A - Demo Board for:LT3497 - Dual Full Function White LED Driver with Integrated Schottky Diodes