The ADP7112 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed signal circuits operating from 20 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection, low noise, and achieves excellent line and load transient response with a small 2.2 ?F ceramic output capacitor. The ADP7112?regulator output noise is 11 ?V rms independent of the output voltage for the fixed options of 5 V or less.The ADP7112?is available in 16 fixed output voltage options. The following voltages are available from stock: 1.2 V (adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V.Each fixed output voltage can be adjusted above the initial set point with an external feedback divider. This allows the ADP7112?to provide an output voltage from 1.2 V to VIN ? VDO with high PSRR and low noise.User programmable soft start with an external capacitor is available in the?ADP7112. The ADP7112?is available in a 6-ball 1 mm ? 1.2mm WLCSP, making it a very compact solution.Applications Regulation to noise sensitive applications ADC, DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADP7157 is an adjustable linear regulator that operates from 2.3 V to 5.5 V and provides up to 1.2 A of output current. Output voltages from 1.2 V to 3.3 V are possible depending on the model. Using an advanced proprietary architecture, the device provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 ?F ceramicoutput capacitor.The ADP7157 is available in four models that optimize powerdissipation and PSRR performance as a function of the inputand output voltage.The typical output noise the ADP7157 regulator is 0.9 ?V rms from 100 Hz to 100 kHz and 1.7 nV/?Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm ?3 mm LFCSP and 8-lead SOIC packages, making it not only avery compact solution, but also providing excellent thermalperformance for applications requiring up to 1.2 A of outputcurrent in a small, low profile footprint.Applications Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links

The ADP7158 is a linear regulator that operates from 2.3 V to 5.5 V and provides up to 2 A of output current. Using an advanced proprietary architecture, it provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 ?F ceramic output capacitor.There are 16 standard output voltages for the ADP7158. The following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V, 2.5 V, 2.8 V, 3.0 V, and 3.3 V. Additional voltages available by special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, and 3.2 V.The ADP7158 regulator typical output noise is 0.9 ?V rms from 100 Hz to 100 kHz and 1.7 nV/?Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7158 is available in a 10-lead, 3 mm ? 3 mm LFCSP and 8-lead SOIC packages, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 2 A of output current in a small, low profile footprint.Applications Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links

The ADP7183 is a complementary metal oxide semiconductor (CMOS), low dropout (LDO) linear regulator that operates from ?2.0 V to ?5.5 V and provides up to ?300 mA of output current. This LDO regulator is ideal for regulation of high performance analog and mixed-signal circuits operating from ?0.5 V down to ?4.5 V. Using an advanced proprietary architecture, the ADP7183 provides high PSRR and low noise, and it achieves excellent line and load transient response with a small 4.7 ?F ceramic output capacitor.The ADP7183 is available in 15 fixed output voltage options. The following voltages are available from stock: ?0.5 V, ?1.0 V,?1.2 V, ?1.5 V, ?1.8 V, ?2.0 V, ?2.5 V, ?3.0 V, and ?3.3 V. Additional voltages available by special order are ?0.8 V, ?0.9 V, ?1.3 V, ?2.8 V, ?4.2 V, and ?4.5 V. An adjustable version is also available that allows output voltages that range from ?0.5 V to ?VIN + 0.5 V with an external feedback divider.The enable logic feature is capable of interfacing with positive or negative logic levels for maximum flexibility.The ADP7183 regulator output noise is 4 ?V rms independent of the output voltage. The ADP7183 is available in an 8-lead, 2 mm ? 2 mm LFCSP, making it not only a very compact solution but also providing excellent thermal performance for applications requiring up to ?300 mA of output current in a small, low profile footprint.Applications Regulation to noise sensitive applications: analog-to-digital converters (ADCs), digital-to-analog converters (DACs), precision amplifiers Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADP8860SHIELD-EVALZ and the ADP8861SHIELD-EVALZ incorporate light emitting diodes (LEDs) for quick and easy evaluation of the ADP8860 and the ADP8861. Note that only the ADP8860SHIELD-EVALZ has dual light intensity sensors. The ADP8860SHIELD-EVALZ and the ADP8861SHIELD-EVALZ follow the form factor of a regular Arduino® shield to allow compatibility with microcontroller boards that use the same interface. These evaluation boards also incorporate a separate header dedicated to I2C communications. The ADP8860 and the ADP8861 are 7-channel LED drivers that utilizes a charge pump with selective gain for maximum efficiency. The LEDs driven by either device are programmable for maximum current and fade in and out times via the I2C interface. Only the ADP8860 has a programable light intensity threshold that can be set via the I2C interface of the device. Each channel can handle up to 30 mA (typical), except for the seventh channel, which can handle 60 mA (typical). Each channel can be unified to have the same fade in time and fade out time, or each channel can have an individual fade in time and fade out time for greater flexibility. For full details on the ADP8860 and the ADP8861, see the ADP8860 and the ADP8861 data sheets, which should be consulted in conjunction with the user guide when using these evaluation boards.

The ADPA1105 is a gallium nitride (GaN), broadband power amplifier that delivers 46 dBm (40 W) with 60% typical power added efficiency (PAE) across a bandwidth of 0.9 GHz to 1.4 GHz. The ADPA1105 provides ?0.5 dB gain flatness across a bandwidth of 0.9 GHz to 1.4 GHz. The ADPA1105 is ideal for pulsed applications such as wireless infrastructure, radar, public mobile radio, and general-purpose amplifications. The ADPA1105 comes in a 32-lead, lead frame chip scale package, premolded cavity (LFCSP_CAV).APPLICATIONSWeather radarMarine radarMilitary radar

The ADPA1107 is a gallium nitride (GaN), broadband power amplifier, delivering 45.0 dBm (35 W) with 56.5% typical power added efficiency (PAE) across a bandwidth of 4.8 GHz to 6.0 GHz. The ADPA1107 provides ?0.5 dB gain flatness from 5.4 GHz to 6.0 GHz.The ADPA1107 is ideal for pulsed applications such as radar, public mobile radio, and general-purpose amplification.The ADPA1107 is housed in a 40-lead, 6 mm ? 6 mm, lead frame chip scale package (LFCSP).APPLICATIONSWeather radarsMarine radarsMilitary radars

ADPA7005AEHZThe ADPA7005 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transfer (pHEMT), monolithic microwave integrated circuit (MMIC), 32 dBm saturated output power (PSAT), >1 W, power amplifier, with an integrated temperature compensated, on-chip power detector that operates between 18 GHz and 44 GHz. The ADPA7005 provides 15.5 dB of small signal gain and approximately 32 dBm of PSAT at 32 GHz from a 5 V supply (see Figure 26 in the data sheet). The ADPA7005 has an output IP3 of 40 dBm between 24 GHz to 34 GHz and is ideal for linear applications such as electronic countermeasure and instrumentation applications requiring >30 dBm of efficient PSAT. The RF input and outputs are internally matched and dc blocked for ease of integration into higher level assemblies. The ADPA7005 is packaged in a 7 mm ? 7 mm, 18?terminal ceramic leadless chip carrier with heat sink (LCC_HS) that exhibits low thermal resistance and is compatible with surface-mount manufacturing techniques.ADPA7005CHIPThe ADPA7005CHIP is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), distributed power amplifier that operates from 20 GHz to 44 GHz. The amplifier provides 17 dB of small signal gain, 31 dBm output power for 1 dB compression (P1dB), and a typical output third-order intercept (IP3) of 41 dBm. The ADPA7005CHIP requires 1200 mA from a 5 V supply on the supply voltage (VDD) and features inputs and outputs that are internally matched to 50 ?, facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via two 0.025 mm wire bonds that are at least 0.31 mm long.Applications Military and space Test instrumentation Communications

The ADRF5045 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 9 kHz to 30 GHz.This broadband switch requires dual supply voltages, +3.3 V and ?3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logiccompatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF5047 is a reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process.The ADRF5047 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.7 dB and an isolation of higher than 31 dB. The device has a radio frequency (RF) input power handling capability of 26.5 dBm for both through path and hot switching.The ADRF5047 draws a low current of 3 ?A on the positive supply of +3.3 V, and ?110 ?A on the negative supply of ?3.3 V. The device provides complementary metal-oxide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)-compatible controls.The ADRF5047 is pin-compatible with the ADRF5046 fast switching version, which operates from 100 MHz to 44 GHz.The ADRF5047 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanner Test instrumentation Cellular infrastructure?mmWave 5G Military radios, radars, and electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5141 is a reflective, single pole double-throw (SPDT) switch manufactured in the silicon process. It is used in transmit-receive (T/R) applications with an integrated power limiter at the receive side. The ADRF5141 operates from 8 GHz to 12 GHz. The RX arm with the integrated power limiter has a limiting capability of 18 dBm output power (TBC) with a low insertion loss of 1.3 dB at 10 GHz while the TX arm has an insertion loss of 0.9 dB at 10 GHz. The ADRF5141 draws a low current of 13 ?A on the positive supply of +3.3 V and 360 ?A on negative supply of ?3.3 V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls. The ADRF5141 requires no additional driver circuitry, making it an ideal alternative to GaN and PIN diode-based switches. The ADRF5141 comes in a 20-lead, 3.0 mm ? 3.0 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +85?.APPLICATIONSElectronic warfareMilitary radios, radars, and electronic counter measuresGaN and PIN diode replacement

The ADRF5300 is a reflective, SPDT switch manufactured in the silicon process.The ADRF5300 is developed for 5G applications ranging from 24 GHz to 32 GHz. The ADRF5300 has a low insertion loss of 1.1 dB, a high isolation of 38 dB, and an RF input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5300 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V (VDD) applied to the VDD pin. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5300 is packaged in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.APPLICATIONSIndustrial scannerTest instrumentationCellular infrastructure: 5G millimeter waveMilitary radios, radars, electronic counter measures (ECMs)Microwave radios and very small aperture terminals (VSATs)

The ADRF5301 is a reflective, single-pole, double-throw (SPDT) switch manufactured in the silicon process.The ADRF5301 was developed for 5G applications from 35 GHz to 44 GHz. This device has low insertion loss of 1.8 dB, high isolation of 28 dB, and radio frequency (RF) input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5301 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V applied to the VDD pin. The devices employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible control.The ADRF5301 is pin-compatible with the ADRF5300, which operates from 24 GHz to 32 GHz.The ADRF5301 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial scanner Test instrumentation Cellular infrastructure mmWave 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) ?

The ADRF5345 is a high linearity, reflective, single-pole, four-throw (SP4T) switch manufactured in the silicon process.The ADRF5345 operates from 1.8 GHz to 3.8 GHz with a typical insertion loss lower than 0.40 dB and a typical input IP3 of 84 dBm. The device has an RF input power handling capability of 39 dBm for continuous wave signals and 39 dBm average and 49 dBm peak for long-term evolution (LTE) signals.The ADRF5345 incorporates an integrated negative voltage generator (NVG) to operate with a single positive supply of 5 V (VDD) applied to the VDD pin drawing a 2 mA supply current. The device employs low voltage complementary metal-oxide semiconductor (LVCMOS)-/low voltage transistor to transistor logic (LVTTL)- compatible controls.The ADRF5345 comes in a 4 mm ? 4 mm, 22-terminal, RoHS-compliant, land grid array (LGA) package and operates between ?40?C to +105?C.APPLICATIONS5G antenna tiltingWireless infrastructureMilitary and high reliability applicationsTest equipmentPin diode replacement

The ADRF5515A is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515A is configured in dual channels with a cascading, two-stage low noise amplifier (LNA) and a high-power silicon singlepole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.05 dB and a high gain of 36 dB at 3.6 GHz, with an output third-order intercept (OIP3) point of 35 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 17 dB of gain at a lower current of 48 mA. In power-down mode, the LNAs are turned off and the device draws 13 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.5 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The device comes in an RoHS-compliant, compact, 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP).APPLICATIONWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems

The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.?In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (

The ADRF6650 is a highly integrated downconverter that integrates dual mixers, dual digital switched attenuators, dual digital variable gain amplifiers, a phase-locked loop (PLL), and voltage controlled oscillators (VCOs). In addition, the ADRF6650 integrates two radio frequency (RF) baluns, serial gain control (SGC) controls, and fast enable inputs for time division duplex (TDD) operation.The on-chip RF baluns enable the ADRF6650 to support 50 ? terminated RF inputs. The integrated passive mixer provides a highly linear downconversion for a 200 MHz, sliding, intermediate frequency (IF) window. The ADRF6650 uses broadband square wave limiting local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this amplifier permits the LO to be applied either above or below the RF input over an extremely wide bandwidth.The ADRF6650 offers two alternatives for generating the differential LO input signal: internally via the on-chip fractional-N synthesizer with low phase noise VCOs, or externally via a low phase noise LO signal. The integrated PLL/VCO enables continuous LO coverage from 450 MHz to 2900 MHz. The PLL referenceinput supports a wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).The ADRF6650 is fabricated using an advanced silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS-compliant, 8 mm ? 8 mm, lead frame chip scale package (LFCSP) package with an exposed pad. Performance is specified over the ?40?C to +105?C maximum paddle temperature.Applications Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells

The ADRF6780 is a silicon germanium (SiGe) design, wideband,microwave upconverter optimized for point to point microwaveradio designs operating in the 5.9 GHz to 23.6 GHz frequencyrange.The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 ? differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.The ADRF6780 upconverter comes in a compact, thermallyenhanced, 5 mm ? 5 mm LFCSP package. The ADRF6780operates over the ?40?C to +85?C temperature range.APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE)

The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations