The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.?In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (

The ADRF6650 is a highly integrated downconverter that integrates dual mixers, dual digital switched attenuators, dual digital variable gain amplifiers, a phase-locked loop (PLL), and voltage controlled oscillators (VCOs). In addition, the ADRF6650 integrates two radio frequency (RF) baluns, serial gain control (SGC) controls, and fast enable inputs for time division duplex (TDD) operation.The on-chip RF baluns enable the ADRF6650 to support 50 ? terminated RF inputs. The integrated passive mixer provides a highly linear downconversion for a 200 MHz, sliding, intermediate frequency (IF) window. The ADRF6650 uses broadband square wave limiting local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this amplifier permits the LO to be applied either above or below the RF input over an extremely wide bandwidth.The ADRF6650 offers two alternatives for generating the differential LO input signal: internally via the on-chip fractional-N synthesizer with low phase noise VCOs, or externally via a low phase noise LO signal. The integrated PLL/VCO enables continuous LO coverage from 450 MHz to 2900 MHz. The PLL referenceinput supports a wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).The ADRF6650 is fabricated using an advanced silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS-compliant, 8 mm ? 8 mm, lead frame chip scale package (LFCSP) package with an exposed pad. Performance is specified over the ?40?C to +105?C maximum paddle temperature.Applications Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells

The ADRF6780 is a silicon germanium (SiGe) design, wideband,microwave upconverter optimized for point to point microwaveradio designs operating in the 5.9 GHz to 23.6 GHz frequencyrange.The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 ? differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.The ADRF6780 upconverter comes in a compact, thermallyenhanced, 5 mm ? 5 mm LFCSP package. The ADRF6780operates over the ?40?C to +85?C temperature range.APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE)

The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The?ADV3221 ?and ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a ?3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than ?58 dB of crosstalk and ?67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The differential gain error of less than 0.02% and differential phase error of less than 0.02?, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 ? back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching.The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on ?5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 envi-ronment.The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) ? ? Data communications ? ? Telecommunications

The ADV3224/ADV3225 are high speed 16 ? 8 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth of greater than 750 MHz and a high slew rate of greater than 2500 V/?s.The ADV3224/ADV3225 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3224 has a gain of +1 and the ADV3225 has a gain of +2, and they both operate on voltage supplies of ?5 V. Channel switching is performed via a serial digital control that can accommodate the daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3224/ADV3225 are available in the 72-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.ApplicationsRouting of high speed signals includingVideo (NTSC, PAL, S, SECAM, YUV, RGB)Compressed video (MPEG, wavelet)3-level digital video (HDB3)Data communicationsTelecommunications

The ADV3226/ADV3227 are high speed 16 ? 16 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth greater than 750 MHz and channel switch times of less than 20 ns with 1% settling.The ADV3226/ADV3227 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3226 has a gain of +1 and the ADV3227 has a gain of +2. They both operate on voltage supplies of ?5 V while consuming only 118 mA (ADV3226) and 133 mA (ADV3227) of idle current. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3226/ADV3227 are available in the 100-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) Data communications Telecommunications

The ADXL203 is a high precision, low power, complete dual-axis accelerometer with signal conditioned voltage outputs, all on a single, monolithic IC. The ADXL203 measures acceleration with a full-scale range of ?1.7 g, ?5 g, or ?18 g. The ADXL203 can measure both dynamic acceleration (for example, vibration) and static acceleration (for example, gravity).The typical noise floor is 110 ?g/?Hz, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (

The ADXL204 is a high precision, low power, complete dual-axis accelerometer with signal-conditioned voltage outputs, all on a single monolithic IC. Like the ADXL203, it measures acceleration with a full-scale range of ?1.7 g; however, the ADXL204 is tested and specified for 3.3 V supply voltage, whereas the ADXL203 is tested and specified at 5 V. Both parts function well over a wide 3 V to 6 V operating voltage range. The ADXL204 can measure both dynamic acceleration (for example, vibration) and static acceleration (for example, gravity).The typical noise floor is 170 ?g/?Hz, allowing signals below 2 mg (0.1? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (

The LTC1286/LTC1298 are micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 250?A of supply current when converting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 5V to 9V supplies. These 12-bit, switched-capacitor, successive approximation ADCs include sample-and-holds. The LTC1286 has a single differential analog input. The LTC1298 offers a software selectable 2-channel MUX.On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers.These circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.Applications Battery-Operated Systems Remote Data Acquisition Battery Monitoring Handheld Terminal Interface Temperature Measurement Isolated Data Acquisition

The LT1304 is a micropower step-up DC/DC converter ideal for use in small, low voltage, battery-operated systems. The devices operate from a wide input supply range of 1.5V to 8V. The LT1304-3.3 and LT1304-5 generate regulated outputs of 3.3V and 5V and the adjustable LT1304 can deliver output voltages up to 25V. Quiescent current, 120?A in active mode, decreases to just 10?A in shutdown with the low-battery detector still active. Peak switch current, internally set at 1A, can be reduced by adding a single resistor from the ILIM pin to ground. The high speed operation of the LT1304 allows the use of small, surface-mountable inductors and capacitors. The LT1304 is available in an 8-lead SO package.Applications 2-, 3-, or 4-Cell to 5V or 3.3V Step-Up Portable Instruments Bar Code Scanners Palmtop Computers Diagnostic Medical Instrumentation Personal Data Communicators/Computers

Demonstration Circuit 1007 is a high efficiency USB power manager with PowerPath™ control and Li-Ion/Polymer battery charger featuring the LTC4088. It includes a synchronous switching input regulator, a full featured battery charger and an ideal diode. Designed specifically for USB applications, the LTC4088’s switching regulator automatically limits its input current to either 100mA, 500mA or 1A for wall-powered applications via logic control. There are also 2.5mA and 500μA suspend modes to prevent the battery from running down when the product is connected to a suspended USB bus. The switching input stage provides power to VOUT where power sharing between the application circuit and the battery charger is managed. Unlike linear PowerPath controllers, the LTC4088’s switching input stage can use nearly all of the 0.5W or 2.5W available from the USB port with minimal power dissipation. This feature allows the LTC4088 to provide more power to the application and battery and eases thermal issues in space constrained applications. An ideal diode ensures that the system power is available from the battery when the input current limit is reached or if the USB or wall supply is removed. The optional external P-channel MOSFET supplements the internal ideal diode by reducing RON and increasing efficiency. A CHRG LED indicates four possible states of the battery charger. Charging is indicated when the LED is steady-ON. Not charging is indicated by a steady-OFF. A NTC fault is indicated by a slow blinking rate (1.5Hz) and a bad battery is indicated by a fast blinking rate (6.1Hz). The LTC4088 is available in the low profile 14-Lead 4mm × 3mm × 0.75mm DFN surface mount package.

DC1012A-C: Demo Board for the LTC2495 16-Bit 8-/16-Channel ΔΣ ADC with PGA, Easy Drive and I2C Interface

DC1017A - Demo Board for: LT5558 - 600MHz to 1100MHz High Linearity Direct Quadrature Modulator

Demonstration circuits 1024A-A and 1024A-B are Micropower Low Noise Boost Converters With Output Disconnect featuring the LT3494 and LT3494A respectively. The demo circuits demonstrate small size and low component count in Boost configuration. Both demo versions are designed to convert a 3V-4.2V source to 15V. The only difference is in the load capability. The 1024A–A supplies 17mA at 3VIN while the 1024A–B supplies 27mA, also at 3VIN. The LT3494 features integrated Schottky diode, output disconnect function, dimming control, output sense resistor and non-audible switching frequency over the entire load range.

DC1027A - Demo Board for LT5560 0.01MHz to 4GHz Low Power Active Mixer

The LTC2928 is a four channel cascadable power supply sequencer and high accuracy supervisor. Sequencing thresholds, order and timing are con?gured with just a few external components, negating the need for PC board layout or software changes during system development. Multiple LTC2928s may be easily connected to sequence an unlimited number of power supplies.Sequence outputs control supply enable pins or N-channel pass gates. Precision input comparators with individual outputs monitor power supply voltages to 1.5% accuracy. Supervisory functions include undervoltage and overvoltage monitoring and reporting as well as ?P reset generation. RST may be forced high to complement margin testing.Application faults, whether internally or externally generated, can shutdown all controlled supplies. The type and source of faults are reported for diagnosis. Individual channel controls are available to independently exercise enable outputs and supervisory functions.A high voltage input allows the LTC2928 to be powered from voltages as high as 16.5V. A buffered reference output permits single negative power supply sequencing and monitoring operations.Applications? Network/Telecom Infrastructure Sequencing for Multiple I/O and Core Voltages Power Management?

Demonstration circuit 1031A-B is a 36V-72Vin, synchronous forward converter featuring the LTC3725 forward converter and the LTC3726 secondary-side controller. This circuit was designed specifically to attain a high current, low ripple, synchronously rectified forward converter to efficiently power 3.3V loads at up to 20A from a typical telecom input voltage range. This circuit features secondary side control of the supply eliminating the need for an optocoupler.

DC1039A-A: Demo Board for the LTC3207 600mA Universal Multi-Output LED/CAM Driver.