Operational Amplifiers - Op Amps VLTG-FDBK, G= 2 CLAMP AMP

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

1.2 A, 20 V, 700 kHz Nonsynchronous Step-down Switching Regulator Features: High efficiency, up to 91% 1.2 A maximum load current ±2% output accuracy over temperature range 700kHz (ADP2300) or 1.4MHz (ADP2301) switching frequency options Wide input voltage range: 3.0 V to 20 V Current-mode control architecture Output voltage from 0.8 V to 0.85×VIN See datasheet for additional features

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays Features: Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect for hot plugging Midscale clamping Power-down mode Low power: 500 mW typical 4:2:2 output format mode

Ultrafast SiGe Voltage Comparator (Featuring Reduced Swing NECL Output Drivers) Features: 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs Features: Wide input supply voltage range: 2.85 V to 15 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 39 V Integrated 2.0 A main switch Optional single-ended primary-inductor converter (SEPIC) configuration for automatic step-up/step-down Inverting regulator to generate VNEG output Adjustable negative output to VIN − 39 V Integrated 1.2 A main switch True shutdown for both positive and negative outputs 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first Out-of-phase operation UVLO, OCP, OVP, and TSD protection 4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP −40°C to +125°C junction temperature range Supported by the ADIsimPower tool set

LC2MOS Complete, High Speed 12-Bit ADC Features:12-Bit Resolution and AccuracyFast Conversion Time- AD7572XX06: 5 µs- AD7572XX12: 12.5 µsComplete with On-Chip ReferenceFast Bus Access Time: 90 nsLow Power: 135 mWSmall, 0.3', 24-Pin Package and28-Terminal Surface Mount Packages

CMOS, 5s 8-Bit Sampling ADC Features: Fast Conversion Time: 5 µs On-Chip Track/Hold Low Total Unadjusted Error: 1 LSB Full Power Signal Bandwidth: 50 kHz Single +5 V Supply 100 ns Data Access Time Low Power (15 mW typ) Low Cost Standard 18-Lead DlPs or 20-Terminal Surface Mount Packages

10-Bit, 1 MSPS, Low-Power A/D Converter in SC70 and MSOP Packages Features: Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW at 1 MSPS with 3 V supplies 12.5 mW at 1 MSPS with 5 V supplies Wide input bandwidth 71 dB SNR at 100 kHz input frequency No pipeline delays Flexible power/serial clock speed management High speed serial interface SPI/QSPI™/MICROWIRE/DSP compatible Standby mode: 1 µA maximum 6-lead SC70 package 8-lead MSOP Qualified for automotive applications

400 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer Features: 400 MSPS internal clock speed Integrated 10-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz at 1 kHz offset (DAC output) Excellent dynamic performance >75 dB SFDR at 160 MHz (±100 kHz offset) AOUT Serial input/output (I/O) control 1.8 V power supply Software and hardware controlled power-down 48-lead TQFP/EP package PLL REFCLK multiplier (4× to 20×) Internal oscillator; can be driven by a single crystal Phase modulation capability Multichip synchronization

CMOS,12-Bit, Monolithic Multiplying DAC Features: Improved version of the obsoleted product, AD7541 Full 4 quadrant multiplication 12-bit linearity (endpoint) All parts guaranteed monotonic TTL/CMOS compatible Protection Schottky diodes not required Low logic input leakage

Tiny 16-Bit SPI nanoDAC+, with 2 (16-Bit) LSB INL and 2 ppm/C Reference Features: Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP High relative accuracy (INL): ±2 LSB maximum at 16 bits AD5683R/AD5682R/AD5681R Low drift, 2.5 V reference: 2 ppm/°C typical Selectable span output: 2.5 V or 5 V Total unadjusted error (TUE): 0.06% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.05% of FSR maximum Low glitch: 0.1 nV-sec High drive capability: 20 mA Low power: 1.2 mW at 3.3 V Independent logic supply: 1.62 V logic compatible Wide operating temperature range: −40°C to +105°C Robust 4 kV HBM ESD protection

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Features: Dual, simultaneous sampling, 14-bit, 2-channel ADC True differential analog inputs Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, ×128 Throughput rate per ADC 1 MSPS for AD7264 Analog input impedance: >1 GΩ Wide input bandwidth −3 dB bandwidth: 1.7 MHz at gain = 2 4 on-chip comparators SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32 Device offset calibration System gain calibration On-chip reference: 2.5 V −40°C to +105°C operation High speed serial interface Compatible with SPI, QSPI™, MICROWIRE™, and DSP 48-lead LFCSP and LQFP packages

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