Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 61.3 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 30 mW per channel at 20 MSPS 63 mW per channel at 80 MSPS Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB 70 dB SNR and 86 dB SFDR Out-of-Range Indicator 28-SOIC and 28-SSOP

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

12-Bit, 1 GSPS/500 MSPS JESD204B,Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs 1.5 W total power per channel at 1 GSPS (default settings) SFDR 79 dBFS at 340 MHz (1 GSPS) 85 dBFS at 340 MHz (500 MSPS) SNR 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS) 65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS) ENOB = 10.4 bits at 10 MHz (1 GSPS) DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS) Noise density −151 dBFS/Hz (1 GSPS) −150 dBFS/Hz (500 MSPS) 1.25 V, 2.5 V, and 3.3 V dc supply operation Low swing full-scale input 1.34 V p-p typical (1 GSPS) 1.63 V p-p typical (500 MSPS) No missing codes Internal ADC voltage reference Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Differential clock input Optional decimate by 2 DDC per channel Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

36V, 600mA Negative Linear Regulator with Programmable Current Limit Features:Output Current: 600mASingle Resistor Sets Output Voltage50μA SET Pin Current: ±1% Initial AccuracyProgrammable Current LimitPositive or Negative Output Current MonitorParallelable for Higher Current and Heat SpreadingLow Dropout Voltage: 300mVLow Output Noise: 18μVRMS (10Hz to 100kHz)Configurable as 3-Terminal Floating RegulatorWide Input Voltage Range: –1.5V to –36VRail-to-Rail Output Voltage Range: 0V to –32VPositive/Negative Shutdown Logic or UVLOProgrammable Cable Drop CompensationLoad Regulation: 1.2mV (1mA to 600mA)Stable with 4.7μF Minimum Output CapacitorStable with Ceramic or Tantalum CapacitorsThermally Enhanced 12-Lead MSOP and 10-Lead 0.75mm × 3mm × 3mm DFN Packages

36V, 1.5A Negative Linear Regulator with Programmable Current Limit Features:Output Current: 1.5ASingle Resistor Sets Output Voltage50μA SET Pin Current: ±1% Initial AccuracyProgrammable Current LimitPositive or Negative Output Current MonitorParallelable for Higher Current and Heat SpreadingLow Dropout Voltage: 300mVLow Output Noise: 18μVRMS (10Hz to 100kHz)Configurable as a 3-Terminal Floating RegulatorWide Input Voltage Range: –1.5V to –36VRail-to-Rail Output Voltage Range: 0V to –32VPositive/Negative Shutdown Logic or UVLOProgrammable Cable Drop CompensationLoad Regulation: 1.2mV (1mA to 1.5A)Stable with 10μF Minimum Output CapacitorStable with Ceramic or Tantalum CapacitorsThermally Enhanced 14-Lead 4mm × 3mm DFN, 16-Lead TSSOP, 7-Lead TO-220 and DD Packages

36V, 1.5A Negative Linear Regulator with Programmable Current Limit Features:Output Current: 1.5ASingle Resistor Sets Output Voltage50μA SET Pin Current: ±1% Initial AccuracyProgrammable Current LimitPositive or Negative Output Current MonitorParallelable for Higher Current and Heat SpreadingLow Dropout Voltage: 300mVLow Output Noise: 18μVRMS (10Hz to 100kHz)Configurable as a 3-Terminal Floating RegulatorWide Input Voltage Range: –1.5V to –36VRail-to-Rail Output Voltage Range: 0V to –32VPositive/Negative Shutdown Logic or UVLOProgrammable Cable Drop CompensationLoad Regulation: 1.2mV (1mA to 1.5A)Stable with 10μF Minimum Output CapacitorStable with Ceramic or Tantalum CapacitorsThermally Enhanced 14-Lead 4mm × 3mm DFN, 16-Lead TSSOP, 7-Lead TO-220 and DD Packages

36V, 1.5A Negative Linear Regulator with Programmable Current Limit Features:Output Current: 1.5ASingle Resistor Sets Output Voltage50μA SET Pin Current: ±1% Initial AccuracyProgrammable Current LimitPositive or Negative Output Current MonitorParallelable for Higher Current and Heat SpreadingLow Dropout Voltage: 300mVLow Output Noise: 18μVRMS (10Hz to 100kHz)Configurable as a 3-Terminal Floating RegulatorWide Input Voltage Range: –1.5V to –36VRail-to-Rail Output Voltage Range: 0V to –32VPositive/Negative Shutdown Logic or UVLOProgrammable Cable Drop CompensationLoad Regulation: 1.2mV (1mA to 1.5A)Stable with 10μF Minimum Output CapacitorStable with Ceramic or Tantalum CapacitorsThermally Enhanced 14-Lead 4mm × 3mm DFN, 16-Lead TSSOP, 7-Lead TO-220 and DD Packages

36V, 1.5A Negative Linear Regulator with Programmable Current Limit Features:Output Current: 1.5ASingle Resistor Sets Output Voltage50μA SET Pin Current: ±1% Initial AccuracyProgrammable Current LimitPositive or Negative Output Current MonitorParallelable for Higher Current and Heat SpreadingLow Dropout Voltage: 300mVLow Output Noise: 18μVRMS (10Hz to 100kHz)Configurable as a 3-Terminal Floating RegulatorWide Input Voltage Range: –1.5V to –36VRail-to-Rail Output Voltage Range: 0V to –32VPositive/Negative Shutdown Logic or UVLOProgrammable Cable Drop CompensationLoad Regulation: 1.2mV (1mA to 1.5A)Stable with 10μF Minimum Output CapacitorStable with Ceramic or Tantalum CapacitorsThermally Enhanced 14-Lead 4mm × 3mm DFN, 16-Lead TSSOP, 7-Lead TO-220 and DD Packages

200mA 2-Terminal Programmable Current Source Features: Programmable 2-Terminal Current Source Maximum Output Current: 200mA Wide Input Voltage Range: 1.2V to 40V Input/Output Capacitors Not Required Resistor Ratio Sets Output Current Initial Set Pin Current Accuracy: 1% Reverse-Voltage Protection Reverse-Current Protection <0.001%/V Line Regulation Typical Current Limit and Thermal Shutdown Protection Available in 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages

200mA 2-Terminal Programmable Current Source Features: Programmable 2-Terminal Current Source Maximum Output Current: 200mA Wide Input Voltage Range: 1.2V to 40V Input/Output Capacitors Not Required Resistor Ratio Sets Output Current Initial Set Pin Current Accuracy: 1% Reverse-Voltage Protection Reverse-Current Protection <0.001%/V Line Regulation Typical Current Limit and Thermal Shutdown Protection Available in 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages

200mA 2-Terminal Programmable Current Source Features: Programmable 2-Terminal Current Source Maximum Output Current: 200mA Wide Input Voltage Range: 1.2V to 40V Input/Output Capacitors Not Required Resistor Ratio Sets Output Current Initial Set Pin Current Accuracy: 1% Reverse-Voltage Protection Reverse-Current Protection <0.001%/V Line Regulation Typical Current Limit and Thermal Shutdown Protection Available in 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages

20V, 200mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator Features: Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) Ultralow Spot Noise: 2.2nV/√Hz at 10kHz Ultrahigh PSRR: 73dB at 1MHz Output Current: 200mA Wide Input Voltage Range: –1.8V to –20V Single Capacitor Improves Noise and PSRR 100µA SET Pin Current: ±1% Initial Accuracy Single Resistor Programs Output Voltage Programmable Current Limit Low Dropout Voltage: 190mV Output Voltage Range: 0V to –19.5V Programmable Power Good and Fast Start-Up Bipolar Precision Enable/UVLO Pin VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR Minimum Output Capacitor: 4.7µF Ceramic 12-Lead MSOP and 3mm × 3mm DFN Packages

20V, 500mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator Features: Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) Ultralow Spot Noise: 2.2nV/√Hz at 10kHz Ultrahigh PSRR: 74dB at 1MHz Output Current: 500mA Wide Input Voltage Range: –1.8V to –20V Single Capacitor Improves Noise and PSRR 100µA SET Pin Current: ±1% Initial Accuracy Single Resistor Programs Output Voltage Programmable Current Limit Low Dropout Voltage: 235mV Output Voltage Range: 0V to –19.5V Programmable Power Good and Fast Start-Up Bipolar Precision Enable/UVLO Pin VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR Minimum Output Capacitor: 10µF Ceramic 12-Lead MSOP and 3mm × 3mm DFN Packages

20V, 500mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator Features: Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) Ultralow Spot Noise: 2.2nV/√Hz at 10kHz Ultrahigh PSRR: 74dB at 1MHz Output Current: 500mA Wide Input Voltage Range: –1.8V to –20V Single Capacitor Improves Noise and PSRR 100µA SET Pin Current: ±1% Initial Accuracy Single Resistor Programs Output Voltage Programmable Current Limit Low Dropout Voltage: 235mV Output Voltage Range: 0V to –19.5V Programmable Power Good and Fast Start-Up Bipolar Precision Enable/UVLO Pin VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR Minimum Output Capacitor: 10µF Ceramic 12-Lead MSOP and 3mm × 3mm DFN Packages

20V, 500mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator Features: Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) Ultralow Spot Noise: 2.2nV/√Hz at 10kHz Ultrahigh PSRR: 74dB at 1MHz Output Current: 500mA Wide Input Voltage Range: –1.8V to –20V Single Capacitor Improves Noise and PSRR 100µA SET Pin Current: ±1% Initial Accuracy Single Resistor Programs Output Voltage Programmable Current Limit Low Dropout Voltage: 235mV Output Voltage Range: 0V to –19.5V Programmable Power Good and Fast Start-Up Bipolar Precision Enable/UVLO Pin VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR Minimum Output Capacitor: 10µF Ceramic 12-Lead MSOP and 3mm × 3mm DFN Packages