The AD536A is a complete monolithic integrated circuit that performs true rms-to-dc conversion. It offers performance comparable or superior to that of hybrid or modular units costing much more. The AD536A directly computes the true rms value of any complex input waveform containing ac and dc components. A crest factor compensation scheme allows measurements with 1% error at crest factors up to 7. The wide bandwidth of the device extends the measurement capability to 300 kHz with less than 3 dB errors for signal levels greater than 100 mV.An important feature of the AD536A, not previously available in rms converters, is an auxiliary dB output pin. The logarithm of the rms output signal is brought out to a separate pin to allow the dB conversion, with a useful dynamic range of 60 dB. Using an externally supplied reference current, the 0 dB level can be conveniently set to correspond to any input level from 0.1 V to 2 V rms.The AD536A is laser trimmed to minimize input and output offset voltage, to optimize positive and negative waveform symmetry (dc reversal error), and to provide full-scale accuracy at 7 V rms. As a result, no external trims are required to achieve the rated unit accuracy.The input and output pins are fully protected. The input circuitry can take overload voltages well beyond the supply levels. Loss of supply voltage with the input connected to external circuitry does not cause the device to fail. The output is short-circuit protected.The AD536A is available in two accuracy grades (J and K) for commercial temperature range (0°C to 70°C) applications, and one grade (S) rated for the −55°C to +125°C extended range. The AD536AK offers a maximum total error of ±2 mV ± 0.2% of reading, while the AD536AJ and AD536AS have maximum errors of ±5 mV ± 0.5% of reading. All three versions are available in a hermetically sealed 14-lead DIP or a 10-pin TO-100 metal header package. The AD536AS is also available in a 20-terminal leadless hermetically sealed ceramic chip carrier.The AD536A computes the true root-mean-square level of a complex ac (or ac plus dc) input signal and provides an equivalent dc output level. The true rms value of a waveform is a more useful quantity than the average rectified value because it relates directly to the power of the signal. The rms value of a statistical signal also relates to its standard deviation.An external capacitor is required to perform measurements to the fully specified accuracy. The value of this capacitor determines the low frequency ac accuracy, ripple amplitude, and settling time.The AD536A operates equally well from split supplies or a single supply with total supply levels from 5 V to 36 V. With 1 mA quiescent supply current, the device is well suited for a wide variety of remote controllers and battery-powered instruments.

The AD536A is a complete monolithic integrated circuit that performs true rms-to-dc conversion. It offers performance comparable or superior to that of hybrid or modular units costing much more. The AD536A directly computes the true rms value of any complex input waveform containing ac and dc components. A crest factor compensation scheme allows measurements with 1% error at crest factors up to 7. The wide bandwidth of the device extends the measurement capability to 300 kHz with less than 3 dB errors for signal levels greater than 100 mV.An important feature of the AD536A, not previously available in rms converters, is an auxiliary dB output pin. The logarithm of the rms output signal is brought out to a separate pin to allow the dB conversion, with a useful dynamic range of 60 dB. Using an externally supplied reference current, the 0 dB level can be conveniently set to correspond to any input level from 0.1 V to 2 V rms.The AD536A is laser trimmed to minimize input and output offset voltage, to optimize positive and negative waveform symmetry (dc reversal error), and to provide full-scale accuracy at 7 V rms. As a result, no external trims are required to achieve the rated unit accuracy.The input and output pins are fully protected. The input circuitry can take overload voltages well beyond the supply levels. Loss of supply voltage with the input connected to external circuitry does not cause the device to fail. The output is short-circuit protected.The AD536A is available in two accuracy grades (J and K) for commercial temperature range (0°C to 70°C) applications, and one grade (S) rated for the −55°C to +125°C extended range. The AD536AK offers a maximum total error of ±2 mV ± 0.2% of reading, while the AD536AJ and AD536AS have maximum errors of ±5 mV ± 0.5% of reading. All three versions are available in a hermetically sealed 14-lead DIP or a 10-pin TO-100 metal header package. The AD536AS is also available in a 20-terminal leadless hermetically sealed ceramic chip carrier.The AD536A computes the true root-mean-square level of a complex ac (or ac plus dc) input signal and provides an equivalent dc output level. The true rms value of a waveform is a more useful quantity than the average rectified value because it relates directly to the power of the signal. The rms value of a statistical signal also relates to its standard deviation.An external capacitor is required to perform measurements to the fully specified accuracy. The value of this capacitor determines the low frequency ac accuracy, ripple amplitude, and settling time.The AD536A operates equally well from split supplies or a single supply with total supply levels from 5 V to 36 V. With 1 mA quiescent supply current, the device is well suited for a wide variety of remote controllers and battery-powered instruments.

The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up, when the supply voltages are changing, VOUT is clamped to 0 V via a low impedance path.The AD5570 DAC comes complete with a set of reference buffers. The reference buffers allow a single, positive reference to be used. The voltage on REFIN is gained up and inverted internally to give the positive and negative reference for the DAC core. Having the reference buffers on-chip eliminates the need for external components such as inverters, precision amplifiers, and resistors, thereby reducing the overall solution size and cost.The AD5570 uses a versatile 3-wire interface that is compatible with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards. Data is presented to the part as a 16-bit serial word. Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DACregister via the SDO pin.Features on the AD5570 include LDAC which is used to update the output of the DAC. The device also has a power-down pin (PD), allowing the DAC to be put into a low power state, and a CLR pin that allows the output to be cleared to 0 V.The AD5570 is available in a 16-lead SSOP.PRODUCT HIGHLIGHTS 1 LSB maximum INL and DNL. Buffered voltage output up to ±14 V. Output controlled during power-up. On-board reference buffers. Wide temperature range of −40°C to +125°C.APPLICATIONS Industrial automation Automatic test equipment Process control Data acquisition systems General-purpose instrumentation

The OP497 is a quad op amp with precision performance in the space-saving, industry standard 16-lead SOlC package. Its combination of exceptional precision with low power and extremely low input bias current makes the quad OP497 useful in a wide variety of applications.Precision performance of the OP497 includes very low offset (120 dB. The OP497 has a power supply rejection of >120 dB which minimizes offset voltage changes experienced in battery-powered systems. The supply current of the OP497 is The OP497 uses a superbeta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at 25°C but double for every 10°C rise in temperature to reach the nanoamp range above 85°C. The input bias current of the OP497 is Combining precision, low power, and low bias current, the OP497 is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photodiode preamplifiers, and long-term integrators. For a single device, see the OP97 data sheet, and for a dual device, see the OP297 data sheet.

The AD585 is a complete monolithic sample-and-hold circuit consisting of a high performance operational amplifier in series with an ultralow leakage analog switch and a FET input integrating amplifier. An internal holding capacitor and matched applications resistors have been provided for high precision and applications flexibility.The performance of the AD585 makes it ideal for high speed 10- and 12-bit data acquisition systems, where fast acquisition time, low sample-to-hold offset, and low droop are critical. The AD585 can acquire a signal to ±0.01% in 3 µs maximum, and then hold that signal with a maximum sample-to-hold offset of 3 mV and less than 1 mV/ms droop, using the on-chip hold capacitor. If lower droop is required, it is possible to add a larger external hold capacitor.The high speed analog switch used in the AD585 exhibits aperture jitter of 0.5 ns, enabling the device to sample full scale (20 V peak-to-peak) signals at frequencies up to 78 kHz with 12-bit precision.The AD585 can be used with any user-defined feedback net-work to provide any desired gain in the sample mode. On-chip precision thin-film resistors can be used to provide gains of +1, -1, or +2. Output impedance in the hold mode is sufficiently low to maintain an accurate output signal even when driving the dynamic load presented by a successive-approximation A/D converter. However, the output is protected against damage from accidental short circuits.The control signal for the HOLD command can be either active high or active low. The differential HOLD signal is compatible with all logic families, if a suitable reference level is provided. An on-chip TTL reference level is provided for TTL compatibility.The AD585 is available in three performance grades. The JP grade is specified for the 0°C to +70°C commercial temperature range and packaged in a 20-pin PLCC. The AQ grade is specified for the -25°C to +85°C industrial temperature range and is packaged in a 14-pin cerdip. The SQ and SE grades are specified for the -55°C to +125°C military temperature range and are packaged in a 14-pin cerdip and 20-pin LCC.

The AD585 is a complete monolithic sample-and-hold circuit consisting of a high performance operational amplifier in series with an ultralow leakage analog switch and a FET input integrating amplifier. An internal holding capacitor and matched applications resistors have been provided for high precision and applications flexibility.The performance of the AD585 makes it ideal for high speed 10- and 12-bit data acquisition systems, where fast acquisition time, low sample-to-hold offset, and low droop are critical. The AD585 can acquire a signal to ±0.01% in 3 µs maximum, and then hold that signal with a maximum sample-to-hold offset of 3 mV and less than 1 mV/ms droop, using the on-chip hold capacitor. If lower droop is required, it is possible to add a larger external hold capacitor.The high speed analog switch used in the AD585 exhibits aperture jitter of 0.5 ns, enabling the device to sample full scale (20 V peak-to-peak) signals at frequencies up to 78 kHz with 12-bit precision.The AD585 can be used with any user-defined feedback net-work to provide any desired gain in the sample mode. On-chip precision thin-film resistors can be used to provide gains of +1, -1, or +2. Output impedance in the hold mode is sufficiently low to maintain an accurate output signal even when driving the dynamic load presented by a successive-approximation A/D converter. However, the output is protected against damage from accidental short circuits.The control signal for the HOLD command can be either active high or active low. The differential HOLD signal is compatible with all logic families, if a suitable reference level is provided. An on-chip TTL reference level is provided for TTL compatibility.The AD585 is available in three performance grades. The JP grade is specified for the 0°C to +70°C commercial temperature range and packaged in a 20-pin PLCC. The AQ grade is specified for the -25°C to +85°C industrial temperature range and is packaged in a 14-pin cerdip. The SQ and SE grades are specified for the -55°C to +125°C military temperature range and are packaged in a 14-pin cerdip and 20-pin LCC.

The AD684 is a monolithic quad sample-and-hold amplifier (SHA). It features four complete sampling channels, each controlled by an independent hold command. Each SHA is complete with an internal hold capacitor. The high accuracy SHA channels are self-contained and require no external components or adjustments. The AD684 is manufactured on a BiMOS process which provides a merger of high performance bipolar circuitry and low power CMOS logic.The AD684 is ideal for high performance, multichannel data acquisition systems. Each SHA channel can acquire a signal in less than 1 µs and retain the held value with a droop rate of less than 0.01 µV/µs. Excellent linearity and ac performance make the AD684 an ideal front end for high speed 12- and 14-bit ADCs.The AD684 has a self-correcting architecture that minimizes hold mode errors and insures accuracy over temperature. Each channel of the AD684 is capable of sourcing 5 mA and incorporates output short circuit protection.The AD684 is specified for three temperature ranges. The J grade device is specified for operation from 0 to +70°C, the A grade from -40°C to +85°C and the S grade from -55°C to +125°C.

The AD7224 is a precision 8-bit, voltage-output, digital-to-analog converter with output amplifier and double buffered interface logic on a monolithic CMOS chip. No external trims are required to achieve full specified performance for the part.The double buffered interface logic consists of two 8-bit registers— an input register and a DAC register. Only the data held in the DAC register determines the analog output of the converter. The double buffering allows simultaneous update in a system containing multiple AD7224's. Both registers may be made transparent under control of three external lines, CS, WR and LDAC. With both registers transparent, the RESET line functions like a zero override; a useful function for system calibration cycles. All logic inputs are TTL and CMOS (5V) level compatible and the control logic is speed compatible with most 8-bit microprocessors.Specified performance is guaranteed for input reference voltages from +2V to +12.5V when using dual supplies. The part is also specified for single supply operation using a reference of +10V. The ouput amplifier is capable of developing +10V across a 2 kΩ load.The AD7224 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC2MOS) process which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip.

The ADV7127 is a high speed, DAC on a single monolithicchip. It consists of a 10-bit, video DAC with an on-board voltagereference, complementary outputs, a standard TTL inputinterface, and high impedance analog output current sources.The ADV7127 has a 10-bit wide input port. A single 5 V or3.3 V power supply and clock are all that are required to makethe device functional.The ADV7127 is fabricated in a complementary metal-oxidesemiconductor (CMOS) process. Its monolithic CMOSconstruction ensures greater functionality with low powerdissipation. The ADV7127 is available in a 24-lead TSSOPpackage which includes a power-down mode and an on-boardvoltage reference circuit.Product Highlights 240 MSPS throughput. Guaranteed monotonic to 10 bits. Compatible with a wide variety of high resolution color graphics systems including RS-343A and RS-170.Applications Digital video systems (1600 × 1200 at 100 Hz) High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Direct digital synthesis (DDS) Wireless local area networks (LANs)

The AD4001/AD4005 are high accuracy, high speed, low power, 16-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4001/AD4005 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2 in the data sheet).Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply.APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems

The AD7616 is a 16-bit, DAS that supports dual simultaneous sampling of 16 channels. The AD7616 operates from a single 5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar input signals while sampling at throughput rates up to 1 MSPS per channel pair with 90.5 dB SNR. Higher SNR performance can be achieved with the on-chip oversampling mode (92 dB for an oversampling ratio (OSR) of 2).The input clamp protection circuitry can tolerate voltages up to ±21 V. The AD7616 has 1 MÙ analog input impedance, regardless of sampling frequency. The single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies.The device contains analog input clamp protection, a dual, 16-bit charge redistribution SAR analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces.The AD7616 is serial peripheral interface (SPI)/QSPI™/DSP/ MICROWIRE compatibleApplications Power line monitoring Protective relays Multiphase motor control Instrumentation and control systems Data acquisition systems (DASs)

The AD7779 is an 8-channel, simultaneous sampling ADC.There are eight full Σ-Δ ADCs on chip. The AD7779 providesan ultralow input current to allow direct sensor connection. Eachinput channel has a programmable gain stage allowing gains of1, 2, 4, and 8 to map lower amplitude sensor outputs into thefull-scale ADC input range, maximizing the dynamic range ofthe signal chain. The AD7779 accepts VREF from 1 V up to 3.6 V.The analog inputs accept unipolar (0 V to VREF/GAIN) or truebipolar (±VREF/GAIN/2 V) analog input signals with 3.3 V or±1.65 V analog supply voltages. The analog inputs can beconfigured to accept true differential, pseudo differential, or singleendedsignals to match different sensor output configurations.Each channel contains an ADC modulator and a sinc3, lowlatency digital filter. An SRC is provided to allow fine resolutioncontrol over the AD7779 ODR. This control can be used inapplications where the ODR resolution is required to maintaincoherency with 0.01 Hz changes in the line frequency. The SRCis programmable through the serial port interface (SPI). TheAD7779 implements two different interfaces: a data outputinterface and SPI control interface. The ADC data outputinterface is dedicated to transmitting the ADC conversionresults from the AD7779 to the processor. The SPI interfaceis used to write to and read from the AD7779 configurationregisters and for the control and reading of data from the SARADC. The SPI interface can also be configured to output theΣ-Δ conversion data.The AD7779 includes a 12-bit SAR ADC. This ADC can be usedfor AD7779 diagnostics without having to decommission one ofthe Σ-Δ ADC channels dedicated to system measurement functions.With the use of an external multiplexer, which can becontrolled through the three general-purpose inputs/outputs pins(GPIOs), and signal conditioning, the SAR ADC can be used tovalidate the Σ-Δ ADC measurements in applications wherefunctional safety is required. In addition, the AD7779 SAR ADCincludes an internal multiplexer to sense internal nodes.The AD7779 contains a 2.5 V reference and reference buffer.The reference has a typical temperature coefficient of 10 ppm/°C.The AD7779 offers two modes of operation: high resolutionmode and low power mode. High resolution mode provides ahigher dynamic range while consuming 10.75 mW per channel;low power mode consumes just 3.37 mW per channel at areduced dynamic range specification.The specified operating temperature range is −40°C to +105°C,although the device is operational up to +125°C.APPLICATIONS Circuit breakers General-purpose data acquisition Electroencephalography (EEG) Industrial process control

The AD9154 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.4 GSPS, permitting multicarrier generation up to the Nyquist frequency in baseband mode. The AD9154 includes features optimized for direct conversion transmit applications including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with the ADRF6720-27 radio frequency quadrature modulator (AQM) from Analog Devices, Inc. In mix mode, the AD9154 DAC can reconstruct carriers in the second and third Nyquist Zones. A serial port interface (SPI) provides the programming/readback of internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9154 is available in two different 88-lead LFCSP packages.PRODUCT HIGHLIGHTS  Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization. Small package size with a 12 mm × 12 mm footprint.APPLICATIONS Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radio Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD9162 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells  FDD and TDD active antenna systems  Microwave, nonline of sight (NLOS) backhaul systems

The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices.The AD9528 generates six outputs (Output 0 to Output 3, Output 12, and Output 13) with a maximum frequency of 1.25 GHz, and eight outputs with a maximum frequency of up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B/JESD204C Low jitter, low phase noise clock distribution ATE and high performance instrumentation

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction field effect transistor (JFET) amplifiers that feature low input noise voltage, current noise, offset voltage, input bias current, and rail-to-rail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is a dual amplifier, and the ADA4610-4 is a quad amplifier.The combination of low offset, noise, and very low input bias current makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. With excellent dc precision, low noise, and fast settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide superior accuracy in medical instruments, electronic measurement, and automated test equipment. Unlike many competitive amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain fast settling performance with substantial capacitive loads. Unlike many older JFET amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. The fast slew rate and great stability with capacitive loads make the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high performance filters. Low input bias currents, low offset, and low noise result in a wide dynamic range for photodiode amplifier circuits. Low noise and distortion, high output current, and excellent speed make the ADA4610-1/ADA4610-2/ ADA4610-4 great choices for audio applications.The ADA4610-1/ADA4610-2/ADA4610-4 are specified over the −40°C to +125°C extended industrial temperature range.The ADA4610-1 is available in an 8-lead SOIC package and in a 5-lead SOT-23 package. The ADA4610-2 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead LFCSP packages. The ADA4610-4 is available in a 14-lead SOIC package and in a 16-lead LFCSP.Applications Instrumentation Medical instruments Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio

The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction field effect transistor (JFET) amplifiers that feature low input noise voltage, current noise, offset voltage, input bias current, and rail-to-rail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is a dual amplifier, and the ADA4610-4 is a quad amplifier.The combination of low offset, noise, and very low input bias current makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. With excellent dc precision, low noise, and fast settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide superior accuracy in medical instruments, electronic measurement, and automated test equipment. Unlike many competitive amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain fast settling performance with substantial capacitive loads. Unlike many older JFET amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. The fast slew rate and great stability with capacitive loads make the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high performance filters. Low input bias currents, low offset, and low noise result in a wide dynamic range for photodiode amplifier circuits. Low noise and distortion, high output current, and excellent speed make the ADA4610-1/ADA4610-2/ ADA4610-4 great choices for audio applications.The ADA4610-1/ADA4610-2/ADA4610-4 are specified over the −40°C to +125°C extended industrial temperature range.The ADA4610-1 is available in an 8-lead SOIC package and in a 5-lead SOT-23 package. The ADA4610-2 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead LFCSP packages. The ADA4610-4 is available in a 14-lead SOIC package and in a 16-lead LFCSP.Applications Instrumentation Medical instruments Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio