14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter Features: JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 434 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS Intermediate frequency (IF) sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range: 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) Serial port control Energy saving power-down modes

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter Features: LVDS digital outputs 1.1 W total power per channel at 500MSPS (default settings) SFDR = 85 dBc at 170MHz fIN (500MSPS) SNR = 68.6 dBFS at 170MHz fIN (500MSPS) ENOB = 10.9 bits at 170 MHz fIN DNL = ±0.5 LSB INL = ±2.5 LSB Noise Density = -153 dBFS/Hz at 500 MSPS 1.25V, 2.50 V and 3.3V supply operation No missing codes Internal analog-to-digital converter (ADC) voltage reference See data sheet for additional features

14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p 1.55 W total power per channel at 2.56 GSPS (default settings) SFDR at 2.56 GSPS encode 73 dBFS at 1.8 GHz AIN at −2.0 dBFS 59 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.56 GSPS encode 59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS 53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SFDR at 2.0 GSPS encode 78 dBFS at 900 MHz AIN at −2.0 dBFS 62 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.0 GSPS encode 62.7 dBFS at 900 MHz AIN at −2.0 dBFS 53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation Programmable FIR filters for analog channel loss equalization 2 integrated, wideband digital processors per channel 48-bit NCO Programmable decimation rates Phase coherent NCO switching Up to 4 channels available Serial port control Supports 100 MHz SPI writes and 50 MHz SPI reads Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs 1.9 W total power per channel (default settings) SFDR = 77 dBFS at 340 MHz SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS) Noise density = −152.6 dBFS/Hz 1.25 V, 2.50 V, and 3.3 V dc supply operation No missing codes 1.58 V p-p differential full scale input voltage Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 1.5 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk See data sheet for additional features 

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 2 W total power at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither AEQ-Q100 qualified for automotive applications

14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 2 W total power at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither AEQ-Q100 qualified for automotive applications

12-Bit, 1200 MSPS DACs Features: Pin-compatible family Excellent dynamic performance LVDS data interface with on-chip 100 Ω terminations Built-in self test LVDS sampling integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supply operation Adjustable analog output 8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) package

12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

14-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SFDR to Nyquist 83 dBc at 5 MHz output 80 dBc at 10 MHz output 73 dBc at 20 MHz output SNR at 5 MHz output, 125 MSPS: 77 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V reference CMOS-compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages Edge-triggered latches

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual, 16-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

16-Bit, 500 MSPS TxDAC+ D/A Converter Features: 16-Bit Resolution with Up to 500 MSPS DAC Update Rate Noise Floor Performance: -164 dBm/Hz @ 20 MHz output IMD to 300 MHz: < -70 dBc DNL: ± 0.75 LSB Selectable 2×/4×/8× High Performance Interpolation Filters: 200 MSPS Data Rate SFDR @ 10 MHz: 86 dBc Direct IF Transmission Frequencies 100-300 MHz and Higher Selectable Data Format:  Twos Complement or Straight Binary LVTTL/CMOS Compatible Inputs Versatile Clock Interface Programmable via SPI Port

4 MHz, 7 nV/Hz, Low Offset and Drift, High Precision Dual Amplifier Features: Offset voltage: 25 μV maximum at 25°C (B grade, 8-lead SOIC, single/ dual)  50 μV maximum at 25°C (A grade, 8-lead SOIC, single/ dual)  50 μV maximum at 25°C (A grade, 14-lead SOIC, quad)  Offset voltage drift: 0.25 μV/°C maximum (B grade, 8-lead SOIC, single/dual)  0.55 μV/°C maximum (A grade, 8-lead SOIC, single/dual)  See data sheet for additional featuresADA4077-EP supports defense and aerospace applications (AQEC standard) Download ADA4077-2-EP Data Sheet (pdf) Extended industrial temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available upon request V62/17604 DSCC Drawing Number

DATA CONVERSION DEVELOPMENT KITS - ADC

DC / DC CONTROLLERS

1.6 Watt Power Amplifier SMT, 0.4 - 2.2 GHz Features: Output IP3: +49 dBm 20.5 dB Gain @ 400 MHz 7.5 dB Gain @ 2100 MHz 41% PAE @ +32.5 dBm Pout +26 dBm CDMA2000 Channel Power @ -45 dBc ACP

I/Q Receiver SMT, 21 - 25 GHz Features: Conversion Gain: 9 dB Image Rejection: 18 dB 2 LO to RF Isolation: 35 dB Noise Figure: 3.5 dB Input IP3: 2 dBm RoHS Compliant 5x5 mm SMT Package