Description

Low Phase Noise, Fast Settling PLL Frequency Synthesizer Features: New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled by 20 µs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF input range up to 3.5 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: –216 dBc/Hz Loop filter design possible using ADIsimPLL™ Qualified for automotive applications