SN65DSI83, SN65DSI84, SN65DSI85 SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide /HPA/ICP/CCI-Consumer_Computer_IF

Current sensing in power supplies and motor controls demand the use of a very low value resistor. Each application varies in need for resistance value power rating size form factor inductance temperature coefficient and accuracy. To meet some of these applications the copper of a printed circuit board (PCB) can be utilized but has some distinct limitations. This design note provides design

Buck Regulator Topologies for Wide Input/Output Voltage Differentials

Supporting HDMI 1.3 12-bit deep color with the TMDS341A

This report describes an all-digital implementation of an AGC on a TMS320C17 DSP. The AGC is designed specifically for modem applications.- The first section provides an overview of modem receiver structure and implementation.- The second section discusses the AGC block diagram and the motivation for using an AGC in a modem receiver.- The third section covers the AGC hardware and s

The first section describes the impact of the clock jitter introduced by the analog phase−locked loop module (ZPLL) on the system clock (SYSCLK) and the peripheral clock (ICLK). In the second section the resulting impact on the CAN communication is explained.

The UCC28019A and its predecessor the UCC28019 are eight-pin active power factor correction (PFC) controllers that use the boost topology and both operate in continuous current conduction mode.

The DP83640 provides a highly precise low-jitter clock output that is frequency-aligned to the masterIEEE 1588 clock and can be phase-aligned as well. Empirical testing shows very low jitter (less than 1 nspeak-to-peak and standard deviation when using the FCO source) and precise phase alignment. Whiletest results show that the FCO has superior long term jitter performance using the PGM as

This application note is intended as a guide for the designer tasked to amplify the small signal from a photodiode or avalanche diode so that it would be large enough for further processing

This application report describes an FIR filter implementation using the MSP430F16x and the MSP430F161x family devices. The complete filter algorithm is executed by the 3-channel DMA peripheral and th

The DSP Hardware Designer's Resource Guide is organized by development flow and functional areas to make your design effort as seamless as possible. Topics covered include getting started, board desi

The UC3907 family of Load Share Controller ICs provides all the necessary features to allow multiple independent power modules to be paralleled so each module supplies only its proportionate share to total load current. Many power supply manufacturers have found it economically feasible to make standard modular power supplies which are easily paralleled for higher current applications. If speci

Since most of the deployed W-CDMA networks use FDD mode only and the W-CDMA FDD has fastclosed-loop power control in both uplink and downlink hardware implementation for RF power detection indownlink from user equipment to base station is needed in order to meet the required air interfacestandard. This application report suggests application subsystem circuits for use in closed-loop power

This technical brief was developed to provide you with details about our 512KFlash memory device that aren?t available in data sheets or application notes.We hope you find this information package helpful and easy to use.

This application report describes a low-cost heart-rate monitor solution based on the MSP430? LaunchPad Value Line Development Kit (<a href=http://focus.ti.com/docs/toolsw/folders/print/msp-exp430g2.h

AB-005 Make a Precision &plusmn; 10 V Reference

With the introduction of the TMS320C2xx (C2xx) family of low-cost digital signal processors (DSPs) many customers are discovering that they can utilize this DSP family for designs that previously required the processing power of a TMS320C5x (C5x) DSP. Although some code has been written for the C2xx reuse of the large repository of C5x application code can dramatically speed up designs using the

This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits recommends when it makes sense to employ them with the FPD-Link II SER/DESshows how to optimally interface them to the SER/DES and discusses distance gains that may berealized with their signal enhancing functions.

This application report implements the Common Public Radio Interface (CPRI) for Remote Radio Heads(RRHs). The designer can use this application report for developing CPRI-based repeater systems inpoint-to-point or multi-hop configurations. This application report consists of:

• Designs for the CPRI SerDes Repeater Boards for the Radio Equipment (RE) and Radio EquipmentController (REC)

The turbo and viterbi coprocessors (TCP/VCP) are programmable peripherals used to decode IS2000/3GPP turbo/viterbi codes. They are integrated into Texas Instruments TMS320C6416 digital signal processor (DSP). Turbo and viterbi decoders lie at the heart of all of the third-generation (3G) wireless standards. Their usage in 3G systems meets the tough bit-error-rate requirements and low signal-to-no