This report describes an all-digital implementation of an AGC on a TMS320C17 DSP. The AGC is designed specifically for modem applications.- The first section provides an overview of modem receiver structure and implementation.- The second section discusses the AGC block diagram and the motivation for using an AGC in a modem receiver.- The third section covers the AGC hardware and s

The first section describes the impact of the clock jitter introduced by the analog phase−locked loop module (ZPLL) on the system clock (SYSCLK) and the peripheral clock (ICLK). In the second section the resulting impact on the CAN communication is explained.

The UCC28019A and its predecessor the UCC28019 are eight-pin active power factor correction (PFC) controllers that use the boost topology and both operate in continuous current conduction mode.

The DP83640 provides a highly precise low-jitter clock output that is frequency-aligned to the masterIEEE 1588 clock and can be phase-aligned as well. Empirical testing shows very low jitter (less than 1 nspeak-to-peak and standard deviation when using the FCO source) and precise phase alignment. Whiletest results show that the FCO has superior long term jitter performance using the PGM as

This document describes two options used to supply power to the Texas Instruments (TI)(tm) TMS320C206 digital signal processor (DSP). The TMS320C206 DSP requires 3.3V for the CPU and 5.0V for the I/O. The first solution applies when a design already has a regulated 5.0V power supply and requires only a 3.3V (LDO) Low Dropout regulator. The second solution applies an unregulated voltage input t

This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:<p><a href=http://wiki.davincidsp.com/index.php/OMAP-L1x/C674

The analog interface circuit (AIC), also called a modem Codec, is a complete data acquisition system on a chip for general-purpose telephony/speech applications such as: modem analog interface, voice-band audio processing, noise cancellation/suppression, hands-free communication, security voice systems, tone generation, echo cancellation, voice-over-internet protocol (VoIP), and industrial process control. The AIC is normally interfaced to a digital signal processor (DSP). This approach has a number of advantages and cost-saving benefits that cannot be realized with traditional Codec analog interfacing. The benefits include:

• lower cost,
• simple interface design and fewer components,
• greater system reliability due to fewer components,
• lower power consumption,
• higher performance, and
• high programmability.

Troika and Synoris Output Selection Filter Guide TPS65250, TPS65251, TPS65252, TPS65253

Reworking LLP Chip Scale Package

When we say that an electric motor is a device that transforms electric power into mechanical power we say two things. First that the motor is ?and behaves as ?a transformer. Second that it stands at the dividing line between electrical and mechanical phenomena. In the case of permanent magnet motors this power transformation works in both directions so that the electrical impedance depends on

High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op amp differential to single-end

This application report presents the basic concept and methodology to develop the TSC2301 touch screen keypad audio and GPIO drivers on the Windows CE (WinCE) operating system (OS). The drivers are not tied to any specific processor platform. They therefore can be called generic and are reusable for any host processor or platform with minimal additional coding.

The EDMA3 is a high-performance multi-channel module for the TMS320C64x+ DSP that allows you to program a wide variety of transfer geometries and sequences. In addition it interacts with the switch central resource (SCR) fabric to compete for bus and read/write access resources. The EDMA3 prioritization scheme is summarized and various program registers are introduced in this application report.

This application note first provides a summary of empirical results found when master to slave node synchronization is measured with Synchronous Ethernet mode enabled. Background information is then provided describing the operation of and topological constraints associated with Synchronous Ethernet mode. Typical applications are then described followed by empirical data which clearly demonstrate

Comparing the PCI2050B to the PCI2050

This application report describes methods to reduce the power consumption of the Hercules™-based microcontrollers and gives indications for the reduction that can be achieved.

All examples and values are based on the xRM48L950ZWTT (Rev. A) microcontroller and are measured on the TI internal silicon checkout board.

Measurement Notes

The measurements were done on non-producti

AN119 - Using an External 32kHz Clock to Drive a CC254x chip

This guide is organized by development flow and functional areas to make your design effort as seamless as possible. Tips on getting started with TMS320C28x™ DSP software and hardware developmen

This application report outlines the implementation of a CPE remote management scheme using the clear EOC Channel. The capabilities of the Clear EOC Channel are discussed for G.dmt different framing mode as well as ADSL2. This application report is meant to be used to provide a basic understanding of the Clear EOC channel and how it might be used for ADSL CPE remote management.