Description

Newer high-speed ADCs come outfitted with a large analog-input bandwidth (about three to six times the maximum sampling frequency) so they can be used in undersampling applications. Recent advances in ADC design extend the usable input range significantly so that system designers can eliminate at least one intermediate frequency stage, which reduces cost and power consumption. In the design of an undersampling receiver, special attention has to be given to the sampling clock, because at higher input frequencies the jitter of the clock becomes a dominant factor in limiting the signal-to-noise ratio (SNR).

Part 1 of this three-part article series focuses on how to accurately estimate jitter from a clock source and combine it with the aperture jitter of the ADC. In Part 2, that combined jitter will be used to calculate the ADC’s SNR, which will then be compared against actual measurements. Part 3 will show how to further increase the SNR of the ADC by improving the ADC’s aperture jitter, with a focus on optimizing the slew rate of the clock signal.