Clock jitter analyzed in the time domain, Part 3

Texas Instruments

Published Date: 09/16/2011

Description

Part 1 of this three-part article series focused on how to accurately estimate jitter from a clock source and combine it with the aperture jitter of an ADC. In Part 2, that combined jitter was used to calculate the ADC’s signal-to-noise ratio (SNR), which was then compared against actual measurements. This article, Part 3, shows how to further increase the SNR of the ADC by improving the ADC’s aperture jitter, with a focus on optimizing the slew rate of the clock signal.

Parts

Part Number Name Companion Part
CDCE72010RGCR CDCE72010RGCR Buy Datasheet
CDCE72010RGCRG4 CDCE72010RGCRG4 Buy Datasheet