Description

In many of today’s high-frequency systems, key specifications are achieved with precise optimizations in the device itself as well as all its peripheral blocks. A thorough understanding and well-designed system with all these components in mind is necessary to attain the best results. This is especially true in applications with RF sampling Analog-to-Digital Converters (ADC), where the sampling clock may use high performance synthesizers to generate very noise high-frequency clock signals. These synthesizers require careful design for the best integrated noise which directly impacts the signal-to-noise ratio (SNR) performance of the ADC. This application report helps understand these performance specifications, show how to approach the optimization process, and provides relevant information to help reach the highest performance levels.