Four TI CMOS clocked first-in first-out (FIFO) memories the 2k?9 SN74ACT807 the 512?18 SN74ACT7803 the 256?18 SN74ACT7805 and the 64?18 SN748ACT7813 provide synchronous interfaces that conform to the requirements of many high-performance systems. The FIFO architecture limits the glue logic necessary and limits the timing constraints to the system. Each FIFO is easily expanded to accommodate var