How to Calculate the Period Jitter from the SSCR for High-Speed ADCs

Texas Instruments

Published Date: 12/17/2003

Description

This document introduces a general formula to translate the phase noise of a clock source rated via the Single Sideband to Carrier Ratio to the cycle-to-cycle jitter of the oscillation period. The link allows to seamlessly aggregate the external clock source phase noise usually given in dBc/Hz to the phase stability figure of the on-chip clock synchronization circuitry usually rated in ps-RMS

Parts

Part Number Name Companion Part
TMS320TCI100 TMS320TCI100 Buy Datasheet
TMS320TCI100GLZ TMS320TCI100GLZ Buy Datasheet
TMX320TCI100BCLZ7 TMX320TCI100BCLZ7 Buy Datasheet