Minimizing Clock Driver Output Skew Using Ganged Outputs

Texas Instruments

Published Date: 01/01/1994

Description

This document helps designers use existing clock-driver products to drive large loads while maintaining a minimum amount of skew between the device outputs. The emphasis of this document is using parallel or ganged outputs to drive loads. A performance evaluation of the CDC201 is provided.

Parts

Part Number Name Companion Part
CDC208DBLE CDC208DBLE Datasheet
CDC208DWR CDC208DWR Buy Datasheet
CDC208DWRG4 CDC208DWRG4 Buy Datasheet
CDC208NS CDC208NS Buy Datasheet
CDC208NSR CDC208NSR Buy Datasheet
CDC208NSRG4 CDC208NSRG4 Buy Datasheet
CDC209DBLE CDC209DBLE Buy Datasheet
CDC209DW CDC209DW Buy Datasheet
CDC209DWR CDC209DWR Buy Datasheet
CDC209N CDC209N Buy Datasheet