Description

This document describes the logic to connect the SPARC Mbus to the TI Futurebus+ (FB+) chipset host interface (HIF). This logic is a translator of Mbus to HIF transactions and vice versa. Direct and paged-memory are described along with techniques for a 64-bit-only data path and a dynamically configurable 32-bit Mbus/32-bit HIF or 64-bit Mbus/64-Bit HIF.