Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
Title | Manufacturer | Published |
---|---|---|
Power-Up Behavior of Clocked Devices (Rev. A) | Texas Instruments | 02/06/2015 |
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | Texas Instruments | 04/01/1996 |