PLL Clock Synthesizer Single 48-Pin VQFN EP T/R
Title | Manufacturer | Published |
---|---|---|
Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev | Texas Instruments | 06/25/2004 |
Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies | Texas Instruments | 12/17/2004 |
Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A) | Texas Instruments | 07/19/2005 |
Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) | Texas Instruments | 12/15/2009 |
General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner | Texas Instruments | 03/21/2003 |
General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) | Texas Instruments | 12/16/2003 |
Basics of the CDC7005 Hold Function | Texas Instruments | 04/13/2006 |
Title | Type | Part number |
---|---|---|
CDCM7005 BGA Package Evaluation Module | Evaluation board | CDCM7005BGA-EVM |