Power Management Reference Design for Xilinx Virtex-6 FPGAs (1.8V @ 2.6A)
Description
The PMP5098 reference design uses four (4) TPS40400 PMBus synchronous buck controllers to regulate and control the Xilinx Virtex-6™ FPGA rails. The output voltages can be dynamically adjusted within a 400mV range with 4mV steps. Additional PMBus control includes: Fsw: ILIM: SS time: UVLO: Thermal Shutdown: ENABLE: PGOOD: UVP: OVP: and OCP modes. The design is ideal for applications that require having design flexibility for the Virtex 6™ four output voltages through PMBus programming: configuration: and control.
Features
- AVS Capability- dynamically adjust Vo through PMBUS: 400mV range with 4mV stepPMBUS Configurability of the power supply parametersDifferential voltage sensingDifferential inductor DCR current sensing200KHz-2MHz prog. fsw: pre-bias start up support Frequency synchronization: and upstream voltage rail tracking
Applications
Product Categories
- Power management
| Download the bill of materials for PMP5098 | Download |
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Download the test file for PMP5098| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| PMP5098 Gerber | 08 May 2014 | ZIP | 33163 | |
| PMP5098 BOM | 09 Jun 2011 | 36 | ||
| PMP5098 Schematic | 09 Jun 2011 | 374 |