Direct Down-Conversion System with I/Q Correction
Description
The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm: which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block: the FPGA includes a digital gain block: a digital power-measurement block: x2 of interpolation block: an I/Q offset correction block: and a quadrature mixing block.
Features
- Direct Down conversion receiver signal chain with automatic IQ correctionIncludes TRF371125 IQ demod for direct conversion to basebandADS5282 to capture the IQ receive signal for IQ processingAutomatic blind IQ correction IP example provided on Altera Cyclone III FPGA
Applications
- Seeker front end
- Global positioning system receiver
- Laser distance meter
- Radar
- Vector signal transceiver (VST)
- Wireless communications test
Product Categories
- RF & microwave
| Download the bill of materials for TIDA-00078 | Download |
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Download the test file for TIDA-00078| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| TIDA-00078 Assembly Drawings (Top and Bottom) | 09 Jun 2014 | ZIP | 2213 | |
| TIDA-00078 BOM | 09 Jun 2014 | 68 | ||
| TIDA-00078 Schematic (TSW6011EVM) | 11 Jul 2013 | 349 |