High Power Density 9V-15V input Intel® Pentium™ N3700 VCC0+VCC1 design for Industrial PC
Description
The TI TPS1623 VR12.1 reference design: supporting Intel® Pentium™ N3700 : uses TI's driverless PWM architecture with TI power stages for high power density: high efficiency: and low component count while meeting Intel voltage tolerance requirements with low ripple: tight loadline: and high output current monitoring accuracy.
Features
- • Meets all Intel® Pentium™ N3700 VCC0+VCC1 rail specifications: including Fast and Slow Dynamic VID transition specs• Driverless PWM architecture with external TI power stages for high effiency and power density• 89% Efficiency at 12VIN: 1.2Vout: 1MHz: at 6.4A output current (VCC0+VCC1)• Load transient performance well within the +/-35mV DC+AC guideline• Only 30x22uF ceramic output caps• 8mV pk-pk output voltage ripple at 12VIN: 6A load: PS0 power state • Meets all Intel® Pentium™ N3700 VCC0+VCC1 rail specifications: including Fast and Slow Dynamic VID transition specs• Driverless PWM architecture with external TI power stages for high effiency and power density
Applications
- Process analytics
Product Categories
- Power management
| Application Area | End Equipment |
|---|---|
| Process analytics | https://www.ti.com/solution/process-analytics#referencedesigns |
| Download the bill of materials for TIDA-00572 | Download |
Design File
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Download the design file for TIDA-00572Test Data
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Download the test file for TIDA-00572| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| TIDA-00572 Gerber | 07 May 2015 | ZIP | 2065 | |
| TIDA-00572 BOM | 07 May 2015 | 321 | ||
| TIDA-00572 Schematic | 07 May 2015 | 2519 |