High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency.
By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization. Finally, schematic, board layout, hardware testing, and results are also presented.
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Download the test file for TIDA-01021Title | Updated | Type | Size (KB) | |
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TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) | 11 Jan 2016 | 6670 | ||
PLL and RF Synthesizer Solutions (Rev. C) | 02 May 2017 | 5293 | ||
TIDA-01021 Gerber (FMC+ to FMC Adapter Card) | 05 Jun 2017 | ZIP | 2095 | |
TIDA-01021 Gerber | 05 Jun 2017 | ZIP | 6503 | |
TIDA-01021 CAD Files (FMC+ to FMC Adapter Card) | 05 Jun 2017 | ZIP | 10215 | |
TIDA-01021 CAD Files | 05 Jun 2017 | ZIP | 7800 | |
TIDA-01021 PCB (FMC+ to FMC Adapter Card) | 05 Jun 2017 | 2765 | ||
TIDA-01021 PCB | 05 Jun 2017 | 6790 | ||
TIDA-01021 Assembly Drawing (FMC+ to FMC Adapter Card) | 05 Jun 2017 | 489 | ||
TIDA-01021 Assembly Drawing | 05 Jun 2017 | 964 | ||
TIDA-01021 BOM (FMC+ to FMC Adapter Card) | 05 Jun 2017 | 26 | ||
TIDA-01021 BOM | 05 Jun 2017 | 84 | ||
TIDA-01021 Schematic and Block Diagram (FMC+ to FMC Adapter Card) | 05 Jun 2017 | 467 | ||
TIDA-01021 Schematic and Block Diagram | 05 Jun 2017 | 1124 |