Description

This reference design demonstrates how to achieve multiple ADC interleaving with high sampling rates and good resolution at low BOM-cost. The reference design was built with electronic imaging systems in mind. High definition imaging and other high speed signal processing applications require ADCs that can achieve high resolution: high SNR: high speed and low power consumption. These requirements cannot always be met with a  single chip. By interleaving multiple SAR ADCs: the design optimizes trade-offs between different ADCs in order to meet all of the system requirements.