Generating AVS SmartReflex core voltage: PMBus for K2E reference design
Description
The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Features
- Provides the AVS SmartReflex Core voltage required by the K2EMeets the 5% voltage requirement for CVDDOperates using the VCNTL interfaceNo voltage converters needed for VCNTL interfaceNo software required for operation
Applications
Product Categories
| Download the bill of materials for TIDEP0041 | Download |
Test Data
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Download the test file for TIDEP0041| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| Generating AVS SmartReflex Core Voltage for K2E BOM | 02 Jul 2015 | 67 | ||
| Generating AVS SmartReflex Core Voltage for K2E Schematic | 02 Jul 2015 | 352 | ||
| K2E Clock Generation Reference Design Layer Plots (PCBs) | 08 Oct 2014 | ZIP | 7495 | |
| K2E Clock Generation Reference Design Gerber | 08 Oct 2014 | ZIP | 26925 |