This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications: based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces: board hardware: software: throughput performance and diagnostic procedures.
Part Number | Name | Companion Part | |
---|---|---|---|
CDCM6208 | CDCM6208 | Buy Datasheet | |
SN74LVC1G07 | SN74LVC1G07 | Buy Datasheet | |
SN74LVC1G08 | SN74LVC1G08 | Buy Datasheet |
Download the bill of materials for TIDEP0070 | Download |
Title | Updated | Type | Size (KB) | |
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TIDEP0070 CAD Files (EVMK2G) | 02 May 2016 | ZIP | 12389 | |
TIDEP0070 Assembly Files (EVMK2G) | 02 May 2016 | ZIP | 151 | |
TIDEP0070 BOM (EVMK2G) | 02 May 2016 | 119 | ||
TIDEP0070 Schematic and Block Diagram (EVMK2G) | 02 May 2016 | 1523 |