DAC Sample and Hold Glitch Reduction Reference Design
Description
DAC R-2R architectures display great performance in regards to noise and accuracy: but at a cost of large glitch area. This design focuses on the reduction of major-carry glitches that occur from code specific transitions in DAC R-2R architectures. This design reduces this glitch area: making it suitable for glitch-sensitive applications such as waveform generation.
Features
- 18-bit: 0-5 V output R-2R DAC with S&H Glitch Reduction Circuitry
Applications
- Oscilloscopes & digitizers
- Battery cell formation & test equipment
- Vector signal transceiver (VST)
- Wireless communications test
Product Categories
- Data converters
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| Download the bill of materials for TIPD142 | Download |
Design File
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Download the design file for TIPD142Test Data
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Download the test file for TIPD142| Title | Updated | Type | Size (KB) | |
|---|---|---|---|---|
| TIPD142 BOM | 09 Sep 2015 | 23 | ||
| TIPD142 Schematic | 09 Sep 2015 | 57 |