Description

Blocking capacitors on supply pins basically have the task of locally short-circuiting the clocked current loop of the digital circuits using a low impedance. This reduces the radiated magnetic field strength and the RF interference currents coupled into the supply voltage level as much as possible. If the capacitors are optimally selected with regard to their impedance curve and geometrically optimally placed at the VCC pins, then the clocked RF current can be blocked in the best possible way.

The technical literature offers extensive theoretical information on correct PCB layout techniques and multi-stage filter & blocking capacitors for supply pins of digital ICs. However, there is often a lack of real measurements or practical simulations. The goal of this AppNote is to show the influence of the MLCC design, the number of ground vias and the placement of the filter components to each other. In addition, it is shown that one can get into unexpected problems with an unfortunate dimensioning of capacitor banks.

To show the various influences in practice, using a four-layer PCB designed exactly for an impedance of 50 Ω, the insertion loss S21 was measured over a wide frequency range from 300 kHz to 3 GHz. Two simulations with the freeware tool LTSpice and the professional tool EMCoS support the observation and show how close one can get to the real measurement using E5071C (ENA RF Network Analyzer) and which influence the via positioning has relative to each other. MMCX types from Würth Elektronik eiSos were used as RF connectors.

Content:

• Circuit diagram and measurement setup
• PCB layout in detail
• LTSpice and EMCoS simulation
• Simulations- & measurement results